Lightening Asynchronous Pipeline Controller Through Resynthesis and Optimization

Abstract

A bundled-data asynchronous circuit is a promising alternative to a synchronous circuit for implementing high performance low power systems, but it requires to deploy special circuitry to support the asynchronous communication between every pair of consecutive pipeline stages. This work addresses the problem of reducing the size of asynchronous pipeline controller. Lightening the pipeline controller directly impacts two critical domains: (1) it mitigates the increase of controller area caused by high process-voltage-temperature variation on circuit; (2) it contributes to proportionally reducing the leakage power. (Note that a long delay in circuit between pipeline stages requires a long chain of delay elements in the controller.) Precisely, we analyze the setup timing paths on the conventional asynchronous pipeline controller, and (i) resynthesize new setup timing paths, which allows to share some of the expensive delay elements among the paths while assuring the communication correctness. Then, we (ii) optimally solve the problem of minimizing the number of delay elements by formulating it into a linear programming. For a set of test circuits with a 45nm standard cell library, it is shown that our synthesis and optimization method reduces the total area of delay elements and the leakage power of pipeline controller by 46.4% and 43.6% on average, respectively, while maintaining the same level of performance and dynamic power consumption.