The 2010 International Conference on Computer Engineering & Systems最新文献

Multimedia system verification through a usage model and a black test box 多媒体系统通过使用模型和黑色测试箱进行验证

The 2010 International Conference on Computer Engineering & Systems Pub Date : 2010-12-23 DOI: 10.1109/ICCES.2010.5674849

D. Marijan, N. Teslic, T. Tekcan, V. Pekovic

引用次数: 1

Delay based routing for real-time traffic in ad hoc networks 基于延迟的自组织网络实时流量路由

The 2010 International Conference on Computer Engineering & Systems Pub Date : 2010-12-23 DOI: 10.1109/ICCES.2010.5674901

D. Darshana, M. Chatterjee, K. Kwiat

引用次数: 5

Performance evaluation of a high throughput crypto coprocessor using VHDL 基于VHDL的高吞吐量加密协处理器性能评估

The 2010 International Conference on Computer Engineering & Systems Pub Date : 2010-12-23 DOI: 10.1109/ICCES.2010.5674859

M. Soliman, Ghada Y. Abozaid

引用次数: 2

Back-to-back converters with doubly fed induction generators for wind energy scheme 风力发电方案双馈感应发电机背靠背变流器

The 2010 International Conference on Computer Engineering & Systems Pub Date : 2010-12-23 DOI: 10.1109/ICCES.2010.5674835

A. Sattar, M. Marei, A. Badr

引用次数: 5

DCT implementation and performance evaluation on a scalable matrix processor 基于可扩展矩阵处理器的DCT实现及性能评价

The 2010 International Conference on Computer Engineering & Systems Pub Date : 2010-12-23 DOI: 10.1109/ICCES.2010.5674882

M. Soliman, A. F. Al-Junaid

{"title":"DCT implementation and performance evaluation on a scalable matrix processor","authors":"M. Soliman, A. F. Al-Junaid","doi":"10.1109/ICCES.2010.5674882","DOIUrl":"https://doi.org/10.1109/ICCES.2010.5674882","url":null,"abstract":"Discrete cosine transform (DCT) is one of the major operations in various image/video compression standards. This paper implements DCT and its inverse (IDCT) on our proposed Mat-Core processor using scalar/vector/matrix instruction sets. Mat-Core extends a general-purpose scalar processor with a matrix unit for processing vector/matrix data. The extended matrix unit is decoupled into two components to hide memory latency: address generation and data computation, which communicate through data queues. The data computation unit is organized in parallel lanes, which can execute scalar-vector, vector-vector, scalar-matrix, vector-matrix, and matrix-matrix instructions. To show the scalability of Mat-Core architecture, the performance of DCT and IDCT are evaluated on Mat-Core with different number of parallel lanes (one, four, and eight lanes). A cycle accurate model of Mat-Core processor is implemented using SystemC (system level modeling language). Our results show performances of 1.5, 5, 6.4 and 14.4 FLOPs/cycle on Mat-Core with single lane and 8-element vector registers, four lanes and 4×4 matrix registers, four lanes and 8×4 matrix registers, and eight lanes and 8×8 matrix registers, respectively. The maximum performance of the Mat-Core processor on DCT and IDCT represents 90% of the ideal value. Moreover, increasing the number of parallel lanes from one to four and then to eight results in speeding up the execution of DCT and IDCT by factors of 4.2 and 9.5, respectively, which indicates the scalability of Mat-Core architecture.","PeriodicalId":124411,"journal":{"name":"The 2010 International Conference on Computer Engineering & Systems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116490863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analysis of binary voting algorithms for use in fault-tolerant and secure computing 二进制投票算法在容错和安全计算中的应用分析

The 2010 International Conference on Computer Engineering & Systems Pub Date : 2010-12-23 DOI: 10.1109/ICCES.2010.5674867

K. Kwiat, Alan D. Taylor, W. Zwicker, Daniel Hill, Sean Wetzonis, Shangping Ren

引用次数: 17

Active fault-tolerant control system 主动容错控制系统

The 2010 International Conference on Computer Engineering & Systems Pub Date : 2010-12-23 DOI: 10.1109/ICCES.2010.5674868

Essam Nabil, Abdel-Azem Sobaih, B. Abou-Zalam

引用次数: 8

Perception of color in 3D Virtual World architectural computer aided design: Impact of color design in student satisfaction 三维虚拟世界建筑计算机辅助设计中的色彩感知:色彩设计对学生满意度的影响

The 2010 International Conference on Computer Engineering & Systems Pub Date : 2010-12-23 DOI: 10.1109/ICCES.2010.5674855

N. Saleeb, Georgios A. Dafoulas

引用次数: 3

Studying the effect of down sampling and spatial interpolation on fractal image compression 研究了下采样和空间插值对分形图像压缩的影响

The 2010 International Conference on Computer Engineering & Systems Pub Date : 2010-12-23 DOI: 10.1109/ICCES.2010.5674885

Ibrahim Ismail, A. Hamdy, Redda Frig

引用次数: 1

Accelerated access to visual data in multimedia applications 多媒体应用程序中可视化数据的加速访问

The 2010 International Conference on Computer Engineering & Systems Pub Date : 2010-12-23 DOI: 10.1109/ICCES.2010.5674848

Shereen Afifi, A. Wahba, Abd-Elmoneim Wahdan

{"title":"Accelerated access to visual data in multimedia applications","authors":"Shereen Afifi, A. Wahba, Abd-Elmoneim Wahdan","doi":"10.1109/ICCES.2010.5674848","DOIUrl":"https://doi.org/10.1109/ICCES.2010.5674848","url":null,"abstract":"To meet the MPEG requirements for high data throughput essential for the recent multimedia applications, new data memory organizations are required. In this paper, a scalable memory organization is proposed to accelerate access to randomly rectangular blocks of visual data to be processed as fast as possible. In the proposed design, we load the video frame pixels stored in traditionally linearly addressable memory as a scan-line manner into a two-dimensional accessible memory, which is organized from a × b memory modules in order to access the entire pixels of the block simultaneously, in parallel. So it is more efficient for multiple blocks access to use the 2D data storage than using the traditionally linearly addressable memory. A module assignment function and an address assignment function are proposed to access any aligned or non-aligned block from the memory modules. The proposed design is implemented and mapped onto an FPGA as a case study. Synthesis results indicate that a scalable, cost-effective design is implemented. High performance is achieved, as at reasonably small hardware costs, considerable speedups of up to 20 thousand times can be expected for the hardware implementation versus the software implementation of the proposed memory organization.","PeriodicalId":124411,"journal":{"name":"The 2010 International Conference on Computer Engineering & Systems","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116423617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0