Performance evaluation of a high throughput crypto coprocessor using VHDL

Abstract

FastCrypto is a general-purpose processor extended with a crypto coprocessor for high throughput encrypting/decrypting data. This paper studies the trade-offs between our proposed FastCrypto performance and its design parameters, including the number of stages per round, the number of parallel AES pipelines, and the size of the queues. Besides, it shows the effect of memory latency on the FastCrypto performance. A throughput of 222 Giga bits per second (Gb/s) at 444 MHz can be achieved on four parallel AES pipelines. To reduce the power consumption, the frequency of the parallel AES pipelines is reduced to 100 MHz while the other components are running at 400 MHz. Our results show a FastCrypto performance of 61.725 bits per clock cycle (b/cc) when 128-bit single port L2 cache memory is used. However, increasing the memory bus width to 256-bit or using 128-bit dual port memory, improves the performance to 112.5 b/cc (45 Gb/s at 400 MHz), which presents 88% of the ideal performance (128 b/cc).