2006 Annual IEEE India Conference最新文献

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Notice of Violation of IEEE Publication Principles The Webcam Mouse: Visual 3D Tracking of Body Features to Provide Computer Access for People with Severe Disabilities 违反IEEE出版原则的通知网络摄像头鼠标:身体特征的视觉3D跟踪,为严重残疾人提供计算机访问
2006 Annual IEEE India Conference Pub Date : 2006-09-01 DOI: 10.1109/INDCON.2006.302809
M. Atyabi, M. Hosseini, M. Mokhtari
{"title":"Notice of Violation of IEEE Publication Principles The Webcam Mouse: Visual 3D Tracking of Body Features to Provide Computer Access for People with Severe Disabilities","authors":"M. Atyabi, M. Hosseini, M. Mokhtari","doi":"10.1109/INDCON.2006.302809","DOIUrl":"https://doi.org/10.1109/INDCON.2006.302809","url":null,"abstract":"The \"Webcam mouse\" system has been developed to provide computer access for people with severe disabilities. The system tracks the computer user's movements with a Webcam and translates them into the movements of the mouse pointer on the screen. Body features such as the tip of the user's nose or finger can be tracked. The visual tracking algorithm is based on cropping an online template of the tracked feature from the current image frame and testing where this template correlates in the subsequent frame. The location of the highest correlation is interpreted as the new location of the feature in the subsequent frame. Various body features are examined for tracking robustness and user convenience. A group of 33 people without disabilities tested the Webcam mouse and quickly learned how to use it to spell out messages or play games. Seven people with severe cerebral palsy or traumatic brain injury have tried the system, five of whom have shown success. They interacted with their environment by spelling out messages and exploring the Internet","PeriodicalId":122715,"journal":{"name":"2006 Annual IEEE India Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117265836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Property Driven Test Generation in Absence of Direct Interface 在没有直接接口的情况下生成属性驱动测试
2006 Annual IEEE India Conference Pub Date : 2006-09-01 DOI: 10.1109/INDCON.2006.302829
B. Pal, P. Dasgupta, P. Chakrabarti
{"title":"Property Driven Test Generation in Absence of Direct Interface","authors":"B. Pal, P. Dasgupta, P. Chakrabarti","doi":"10.1109/INDCON.2006.302829","DOIUrl":"https://doi.org/10.1109/INDCON.2006.302829","url":null,"abstract":"This paper presents an automatic test generation methodology for complex coverage points in the context of systems consisting of an environment (E), a machine (M) and a controller (C). The coverage points are modeled as temporal scenarios over a set of low-level events supported in M. These events can't be generated directly. There exists a set of high-level macros (supported in E) that can generate these events. The objective is to generate a sequence of macros to reach a complex coverage point in M. We present a prototype tool that automatically generates a systemverilog test-bench for the required macro sequence generation. The result on DLX pipeline shows the effectiveness of the approach","PeriodicalId":122715,"journal":{"name":"2006 Annual IEEE India Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128367053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Detection of Diabetic Retinopathy in Fundus Images using Vector Quantization Technique 利用矢量量化技术检测眼底图像中的糖尿病视网膜病变
2006 Annual IEEE India Conference Pub Date : 2006-09-01 DOI: 10.1109/INDCON.2006.302806
D. Satyarthi, Biju Raju, S. Dandapat
{"title":"Detection of Diabetic Retinopathy in Fundus Images using Vector Quantization Technique","authors":"D. Satyarthi, Biju Raju, S. Dandapat","doi":"10.1109/INDCON.2006.302806","DOIUrl":"https://doi.org/10.1109/INDCON.2006.302806","url":null,"abstract":"Diabetic retinopathy is one of the major cause of blindness among the people. Many approaches are proposed by the authors to automate and detect the presence of diabetic retinopathy in fundus image. We propose a novel method of detection of the diabetic retinopathy using Gaussian intensity feature input to a VQ classifier. The underlying idea of using this technique in fundus imaging is that there are certain features which pertain only to diabetic retinopathy. These features are extracted in terms of diameter of the blood vessels expressed by sigma, and the height of the Gaussian profile across the cross-section, given by h. In this work, 30 images are taken as normal images and 25 pathological images are considered. A successful average diagnostic performance of 90% is achieved in this method","PeriodicalId":122715,"journal":{"name":"2006 Annual IEEE India Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127125403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Image Segmentation using Global and Local Fuzzy Statistics 基于全局和局部模糊统计的图像分割
2006 Annual IEEE India Conference Pub Date : 2006-09-01 DOI: 10.1109/INDCON.2006.302813
D. Sen, S. Pal
{"title":"Image Segmentation using Global and Local Fuzzy Statistics","authors":"D. Sen, S. Pal","doi":"10.1109/INDCON.2006.302813","DOIUrl":"https://doi.org/10.1109/INDCON.2006.302813","url":null,"abstract":"In this paper, criterion optimization based image thresholding techniques to perform segmentation using global and local fuzzy statistics are presented. The global and local fuzzy statistics considered for an image are the fuzzy histogram and fuzzy co-occurrence matrix of the image, respectively. A novel way of adapting the membership function, which is required to calculate the fuzzy statistics, to the local nature of the corresponding crisp first-order statistic (histogram) is suggested. The fuzzy statistics of an image obtained using such an adaptive membership function are called adaptive fuzzy statistics. Experimental results of various image segmentation techniques using crisp, fuzzy and the proposed adaptive fuzzy statistics are given. A comparative study demonstrating the usefulness of fuzzy statistics in image segmentation and the effectiveness of adapting the membership function in order to determine the fuzzy statistics is presented","PeriodicalId":122715,"journal":{"name":"2006 Annual IEEE India Conference","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127398206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Reconfigurable Architecture For WTLS WTLS的可重构架构
2006 Annual IEEE India Conference Pub Date : 2006-09-01 DOI: 10.1109/INDCON.2006.302835
R. Seshasayanan, K. Senthil Kumar
{"title":"Reconfigurable Architecture For WTLS","authors":"R. Seshasayanan, K. Senthil Kumar","doi":"10.1109/INDCON.2006.302835","DOIUrl":"https://doi.org/10.1109/INDCON.2006.302835","url":null,"abstract":"The rapidly growth of the transmitted data amount, over wireless networks, has triggered special needs for compression, in an attempt for real-time communications. wireless transport layer security (WTLS) is the security layer for both wireless application protocol and open mobile alliance. In spite of the fact that a great, a compression unit is optional. Compression in wireless portable devices is a sensitive issue due to the restricted resources environment. The composite compression encoders allocate area that system can not support. In this paper, an area optimized multi coder-processor is proposed for the WTLS. The proposed system consists of three units and serves three different types of compression: speech (ADPCM), test (Huffman) and image (RLE). The proposed processor minimizes the area resources compared with other published works and has competitive performance. The paper deals with reconfiguration of any of the compression technique at any point of time","PeriodicalId":122715,"journal":{"name":"2006 Annual IEEE India Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129033076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An Active Rule approach for Network Intrusion Detection with NeuroC4.5 Algorithm 基于neuro4.5算法的主动规则网络入侵检测方法
2006 Annual IEEE India Conference Pub Date : 2006-09-01 DOI: 10.1109/INDCON.2006.302774
S.S. Sivatha Sindhu, S. Geetha, S. Subashini, R. Vijaya Priya, A. Kannan
{"title":"An Active Rule approach for Network Intrusion Detection with NeuroC4.5 Algorithm","authors":"S.S. Sivatha Sindhu, S. Geetha, S. Subashini, R. Vijaya Priya, A. Kannan","doi":"10.1109/INDCON.2006.302774","DOIUrl":"https://doi.org/10.1109/INDCON.2006.302774","url":null,"abstract":"Information systems are one of the most rapidly changing and vulnerable systems, where security is a major issue. The number of security-breaking attempts originated inside the organizations is increasing steadily. Attacks made in this way, usually done by \"authorized\" users of the system cannot be immediately traced. As the idea of filtering the traffic at the entrance door, by using firewalls and the like, is not completely successful, the use of intrusion detection systems should be considered to increase the defense capacity of an information system. This paper presents a NeuroC4.5 based approach to network intrusion detection to detect anomalies in the computer networks. Decision tree is with good comprehensibility while neural network is with strong generalization ability. So, these merits are integrated into a novel decision tree algorithm NeuroC4.5. The NeuroC4.5 is employed to derive a set of classification rules from network audit data. The generated rules are then used to detect network intrusions in a real-time environment. Unlike most existing decision tree based approaches, the spawned rules are more effective because the generalization ability of NeuroC4.5 decision trees is better than that of C4.5 decision trees. A comparative evaluation of the proposed NeuroC4.5 model with the classical C4.5 algorithm, on audit data set provided by MIT Lincoln labs, has been presented; superior detection accuracy has been reported by our proposed model","PeriodicalId":122715,"journal":{"name":"2006 Annual IEEE India Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121287518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Implementation Aspects of Software Development Projects 软件开发项目的实现方面
2006 Annual IEEE India Conference Pub Date : 2006-09-01 DOI: 10.1109/INDCON.2006.302750
Sandhya Kakkar
{"title":"Implementation Aspects of Software Development Projects","authors":"Sandhya Kakkar","doi":"10.1109/INDCON.2006.302750","DOIUrl":"https://doi.org/10.1109/INDCON.2006.302750","url":null,"abstract":"The software industry has been plagued by the staggering failure rate of projects, which have resulted in the loss of billions of dollars. The industry has realized that the solution lies in fixing the software process. Hence the processes have been built for development of the systems. The implementation process has still not gained that much importance. Hence problems are faced in moving the systems to production. This paper talks of the implementation/operational aspects. The failure of projects is now being owed to customer not having the correct vision & strategy for the developed software product. The customer blames it to the IT company for developing the 'not so good' product. The fix lies in the IT companies to handhold with the customers on this aspect, guide them throughout on the process of implementation, extend its support for implementation of the product with getting the right involvement and support from the customer during implementation. The implementation of the developed software product is a collaborative effort between the customer and the developer","PeriodicalId":122715,"journal":{"name":"2006 Annual IEEE India Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125700131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
High Gain and Efficient Patch Antenna on Micromachined GaAs EBGs with Increased Bandwidth 微机械GaAs ebg的高增益高效贴片天线
2006 Annual IEEE India Conference Pub Date : 2006-09-01 DOI: 10.1109/INDCON.2006.302800
D. Dey, R. S. Kshetrimayum
{"title":"High Gain and Efficient Patch Antenna on Micromachined GaAs EBGs with Increased Bandwidth","authors":"D. Dey, R. S. Kshetrimayum","doi":"10.1109/INDCON.2006.302800","DOIUrl":"https://doi.org/10.1109/INDCON.2006.302800","url":null,"abstract":"Microstrip antennas find widespread use in communication systems because of its small size, low weight and low manufacturing cost. The current trend in communication circuitry is on chip integration of all circuit elements. This achieves a faster data transmission rate and compact design with high density layouts. To achieve faster data rate and to realize more compact devices antenna fabrication should be done on chip. In this paper we have investigated two different techniques for microstrip antenna performance enhancement namely micromachining and EBG substrates. Our proposed antenna design uses both of these techniques together on the same substrate. The results demonstrate that the proposed design has far better performance in terms of peak directivity, peak gain and bandwidth","PeriodicalId":122715,"journal":{"name":"2006 Annual IEEE India Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116062419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An Improved Fuzzy Mechanism for 3D Soccer Simulation Agent's Shoot Skill 一种改进的三维足球仿真Agent射门技术模糊机制
2006 Annual IEEE India Conference Pub Date : 2006-09-01 DOI: 10.1109/INDCON.2006.302811
M. Mozafari, A. M. Fard, V. Salmani, Mahmoud Naghibzadeh
{"title":"An Improved Fuzzy Mechanism for 3D Soccer Simulation Agent's Shoot Skill","authors":"M. Mozafari, A. M. Fard, V. Salmani, Mahmoud Naghibzadeh","doi":"10.1109/INDCON.2006.302811","DOIUrl":"https://doi.org/10.1109/INDCON.2006.302811","url":null,"abstract":"RoboSoccer simulation is a complex multi-agent system in which agents play the role of soccer players and the main goal is to have a perfect domain for research and investigation on artificial intelligence. This paper intends to propose a new scoring module to select the best point on the goal line to shoot, considering player's position, catching and shooting time difference, and distance to target. Two different approaches have been implemented for this purpose. The first one is a simple decision making policy and the latter one takes advantage of statistical measurement and fuzzy decision making. Results show the superiority of the proposed method performance in over our previous work implemented on Nexus 3D RoboSuccer team of Ferdowsi University","PeriodicalId":122715,"journal":{"name":"2006 Annual IEEE India Conference","volume":"56 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132575543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
High Throughput, low cost, Fully Pipelined Architecture for AES Crypto Chip 高吞吐量,低成本,全流水线架构的AES加密芯片
2006 Annual IEEE India Conference Pub Date : 2006-09-01 DOI: 10.1109/INDCON.2006.302814
N. Iyer, P. Anandmohan, D. Poornaiah, V. Kulkarni
{"title":"High Throughput, low cost, Fully Pipelined Architecture for AES Crypto Chip","authors":"N. Iyer, P. Anandmohan, D. Poornaiah, V. Kulkarni","doi":"10.1109/INDCON.2006.302814","DOIUrl":"https://doi.org/10.1109/INDCON.2006.302814","url":null,"abstract":"Reprogrammable devices such as field programmable gate arrays (FPGA's) are highly attractive options for hardware implementations of encryption algorithms. This paper proposes compact, memory less, high-speed hardware architectures for the Rijndael AES encryptor/decryptor, with combined data path, resource sharing and logic optimization for novel networking applications. Architectural optimization exploits the strength of pipelining, loop unrolling and sub-pipelining. Speed is increased by processing multiple rounds simultaneously at the cost of increased area. Algorithmic optimization exploits algorithmic strength inside each round unit. Various methods such as resource sharing and common sub expression elimination method for realizing various transformations in each round unit are presented to reduce the critical path and area issues between encryptor, and decryptor, advantage of sub-pipelining can be further explored by eliminating the unbreakable delay incurred by look-up tables in the conventional approaches, the widely used implementation of S-box, which uses combinational logic only. We explore the use of subfield arithmetic for efficient implementations of Galois Field arithmetic such as multiplication and inversion. Our technique involves mapping field elements to a composite field representation and a representation technique which minimizes the computation cost of the relevant arithmetic. Our method results in a very compact and fast gate circuit for Rijndael encryption and decryption. The pipelined architecture can be made to toggle between the encryption and decryption modes without the presence of any dead cycle. Using the proposed architecture, a fully sub-pipelined AES-128 core with both inner and outer round pipelining and a 5 sub-stages in each round unit implemented using Virtex-E devices can achieve a throughput of 26.64 Gbps at 206.84 MHz and 11720 CLB Slices in non-feedback modes with reduction of reconfigurable logic area of the complete cipher by up to 30%., and S-box with 64% reduction in area, which is faster and more efficient than the fastest previous FPGA implementation known to date","PeriodicalId":122715,"journal":{"name":"2006 Annual IEEE India Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121888349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
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