2019 Conference on Design and Architectures for Signal and Image Processing (DASIP)最新文献

Mapping and Frequency Joint Optimization for Energy Efficient Execution of Multiple Applications on Multicore Systems 多核系统多应用节能执行的映射与频率联合优化

2019 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2019-10-01 DOI: 10.1109/DASIP48288.2019.9049177

Simei Yang, S. L. Nours, M. M. Real, S. Pillement

引用次数: 2

Speeding-up CNN inference through dimensionality reduction 通过降维加速CNN推理

2019 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2019-10-01 DOI: 10.1109/DASIP48288.2019.9049204

Lucas Fernández Brillet, N. Leclaire, S. Mancini, Sébastien Cleyet-Merle, M. Nicolas, Jean-Paul Henriques, C. Delnondedieu

引用次数: 1

Using Time-of-Flight Sensors for People Counting Applications 使用飞行时间传感器计数应用

2019 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2019-10-01 DOI: 10.1109/DASIP48288.2019.9049169

Michal Stec, Viktor Herrmann, B. Stabernack

{"title":"Using Time-of-Flight Sensors for People Counting Applications","authors":"Michal Stec, Viktor Herrmann, B. Stabernack","doi":"10.1109/DASIP48288.2019.9049169","DOIUrl":"https://doi.org/10.1109/DASIP48288.2019.9049169","url":null,"abstract":"Precisely detecting and counting people who are using public transportation is one of the key methods for predicting and planning an efficient use of buses, trams and trains. Providing an effective, well-planned public transportation service is not only important for economic reasons. It also helps to tackle a variety of environmental problems and contributes to a reduction of traffic congestion in urban areas. A couple of such systems had been developed in the past. Those were not sufficiently precise, however. In most cases, these systems rely on data processing generated by one particular type of a 2D image sensor. In this paper we present a robust people counting application, which runs on embedded systems with reasonable requirements as far as computational power is concerned and relies on the processing of 3D data generated by a Time-of-Flight (ToF) sensor. Processing of time-of-flight data requires a couple of preprocessing steps, which is crucial for the subsequent people detection, tracking and counting algorithms. The influence of these preprocessing steps and the effect on the developed detection algorithm are presented. Methods of avoiding misinterpretations by the detection algorithms are discussed. A detailed description of the core algorithms which were developed to process 3D data is provided. An overview will be given on how this method could be further enhanced for the purpose of detecting and differentiating vital and non-vital objects.","PeriodicalId":120855,"journal":{"name":"2019 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131089085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

FPGA-Based Acceleration of Expectation Maximization Algorithm Using High-Level Synthesis 基于fpga的期望最大化加速高级综合算法

2019 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2019-10-01 DOI: 10.1109/DASIP48288.2019.9049183

M. A. Momen, Mohammed A. S. Khalid, Mohammad Abdul Moin Oninda

{"title":"FPGA-Based Acceleration of Expectation Maximization Algorithm Using High-Level Synthesis","authors":"M. A. Momen, Mohammed A. S. Khalid, Mohammad Abdul Moin Oninda","doi":"10.1109/DASIP48288.2019.9049183","DOIUrl":"https://doi.org/10.1109/DASIP48288.2019.9049183","url":null,"abstract":"Expectation Maximization (EM) is a soft clustering algorithm which partitions data iteratively into M clusters. It is one of the most popular data mining algorithms that uses Gaussian Mixture Models (GMM) for probability density modeling and is widely used in applications such as signal processing and Machine Learning (ML). EM requires high computation time when dealing with large data sets. This paper presents an optimized implementation of EM algorithm on Stratix V and Arria 10 FPGAs using Intel FPGA Software Development Kit (SDK) for Open Computing Language (OpenCL). Comparison of performance and power consumption between Central Processing Unit (CPU), Graphics Processing Unit (GPU) and FPGA is presented for various dimension and cluster sizes. Compared to Intel® Xeon® CPU E5-2637, our fully optimized OpenCL model for EM targeting Arria 10 FPGA achieved up to 1000x speedup in terms of throughput (T) and 5395x speedup in terms of throughput per unit of power consumed (T/P). Compared to previous research on EM-GMM implementation on GPUs, Arria 10 FPGA obtained up to 64.74x speedup (T) and 486.78x speedup (T/P).","PeriodicalId":120855,"journal":{"name":"2019 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134283604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A New Real-Time Embedded Video Denoising Algorithm 一种新的实时嵌入式视频去噪算法

2019 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2019-10-01 DOI: 10.1109/DASIP48288.2019.9049189

Andrea Petreto, Thomas Romera, F. Lemaitre, I. Masliah, B. Gaillard, Manuel Bouyer, Quentin L. Meunier, L. Lacassagne

{"title":"A New Real-Time Embedded Video Denoising Algorithm","authors":"Andrea Petreto, Thomas Romera, F. Lemaitre, I. Masliah, B. Gaillard, Manuel Bouyer, Quentin L. Meunier, L. Lacassagne","doi":"10.1109/DASIP48288.2019.9049189","DOIUrl":"https://doi.org/10.1109/DASIP48288.2019.9049189","url":null,"abstract":"Many embedded applications rely on video processing or on video visualization. Noisy video is thus a major issue for such applications. However, video denoising requires a lot of computational effort and most of the state-of-the-art algorithms cannot be run in real-time at camera framerate. This article introduces a new real-time video denoising algorithm for embedded platforms called RTE-VD. We first compare its denoising capabilities with other online and offline algorithms. We show that RTE-VD can achieve real-time performance (25 frames per second) for qHD video (960⨯540 pixels) on embedded CPUs and the output image quality is comparable to state-of-the-art algorithms. In order to reach real-time denoising, we applied several high-level transforms and optimizations (SIMDization, multi-core parallelization, operator fusion and pipelining). We study the relation between computation time and power consumption on several embedded CPUs and show that it is possible to determine different frequency and core configurations in order to minimize either the computation time or the energy.","PeriodicalId":120855,"journal":{"name":"2019 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114957376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

POLYCiNN: Multiclass Binary Inference Engine using Convolutional Decision Forests POLYCiNN:使用卷积决策森林的多类二元推理引擎

2019 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2019-10-01 DOI: 10.1109/DASIP48288.2019.9049176

A. Abdelsalam, A. Elsheikh, J. David, Pierre Langlois

{"title":"POLYCiNN: Multiclass Binary Inference Engine using Convolutional Decision Forests","authors":"A. Abdelsalam, A. Elsheikh, J. David, Pierre Langlois","doi":"10.1109/DASIP48288.2019.9049176","DOIUrl":"https://doi.org/10.1109/DASIP48288.2019.9049176","url":null,"abstract":"Convolutional Neural Networks (CNNs) have achieved significant success in image classification. One of the main reasons that CNNs achieve state-of-the-art accuracy is using many multi-scale learnable windowed feature detectors called kernels. Fetching of kernel feature weights from memory and performing the associated multiply and accumulate computations consume massive amount of energy. This hinders the widespread usage of CNNs, especially in embedded devices. In comparison with CNNs, decision forests are computationally efficient since they are composed of decision trees, which are binary classifiers by nature and can be implemented using AND-OR gates instead of costly multiply and accumulate units. In this paper, we investigate the migration of CNNs to decision forests as one of the promising approaches for reducing both execution time and power consumption while achieving acceptable accuracy. We introduce POLYCiNN, an architecture composed of a stack of decision forests. Each decision forest classifies one of the overlapped sub-images of the original image. Then, all decision forest classifications are fused together to classify the input image. In POLYCiNN, each decision tree is implemented in a single 6-input Look-Up Table and requires no memory access. Therefore, POLYCiNN can be efficiently mapped to simple and densely parallel hardware designs. We validate the performance of POLYCiNN on the benchmark image classification tasks of the MNIST, CIFAR-10 and SVHN datasets.","PeriodicalId":120855,"journal":{"name":"2019 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128860285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hybrid Prototyping Methodology for Rapid System Validation in HW/SW Co-Design 硬件/软件协同设计中快速系统验证的混合原型方法

2019 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2019-10-01 DOI: 10.1109/DASIP48288.2019.9049195

Arief Wicaksana, A. Charif, Caaliph Andriamisaina, N. Ventroux

{"title":"Hybrid Prototyping Methodology for Rapid System Validation in HW/SW Co-Design","authors":"Arief Wicaksana, A. Charif, Caaliph Andriamisaina, N. Ventroux","doi":"10.1109/DASIP48288.2019.9049195","DOIUrl":"https://doi.org/10.1109/DASIP48288.2019.9049195","url":null,"abstract":"As the System-on-Chip (SoC) complexity increases, hardware/software co-design plays an important role to improve design productivity, reduce time to market, and optimize the overall results. Consequently, there is a high interest in providing rapid system validation in such a paradigm to achieve the aforementioned objectives. There exist in previous works prototyping techniques related to the development phase. FPGA-based prototyping has the benefits of enabling HW/SW integration and system validation after the Register Transfer Level (RTL) implementation is available while virtual platforms provide capabilities to accelerate software development with higher level functional models, e.g. Transaction Level Modeling (TLM). In this paper, we propose a hybrid prototyping methodology which takes advantage of virtual and FPGA-based prototyping in a single framework. We aim to provide a rapid and flexible system validation solution for HW/SW co-design at various stages of development based on the availability of TLM and RTL implementations. The proposed methodology allows online and offline performance analysis and debugging for early feedback in HW/SW architecture exploration. This was evaluated in the experiments with a neural network processor as a case study.","PeriodicalId":120855,"journal":{"name":"2019 Conference on Design and Architectures for Signal and Image Processing (DASIP)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133484526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Real-Time Implementation of Adaptive Correlation Filter Tracking for 4K Video Stream in Zynq UltraScale+ MPSoC 在Zynq UltraScale+ MPSoC中实时实现4K视频流的自适应相关滤波器跟踪

2019 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2019-10-01 DOI: 10.1109/DASIP48288.2019.9049203

M. Kowalczyk, Dominika Przewlocka, T. Kryjak

引用次数: 3

Run-Time Coarse-Grained Hardware Mitigation for Multiple Faults on VLIW Processors 针对VLIW处理器多故障的运行时粗粒度硬件缓解

2019 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2019-10-01 DOI: 10.1109/DASIP48288.2019.9049194

Rafail Psiakis, A. Kritikakou, O. Sentieys, E. Casseau

引用次数: 0

Distilling the knowledge in CNN for WCE screening tool 提炼CNN中的知识用于WCE筛选工具

2019 Conference on Design and Architectures for Signal and Image Processing (DASIP) Pub Date : 2019-10-01 DOI: 10.1109/DASIP48288.2019.9049201

Thomas Garbay, Orlando Chuquimia, A. Pinna, H. Sahbi, X. Dray, B. Granado

引用次数: 2