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8th Euromicro Conference on Digital System Design (DSD'05)最新文献

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P2I: an innovative MDA methodology for embedded real-time system P2I:嵌入式实时系统的创新MDA方法论
8th Euromicro Conference on Digital System Design (DSD'05) Pub Date : 2005-08-30 DOI: 10.1109/DSD.2005.61
A. Cuccuru, R. Simone, T. Saunier, G. Siegel, Y. Sorel
{"title":"P2I: an innovative MDA methodology for embedded real-time system","authors":"A. Cuccuru, R. Simone, T. Saunier, G. Siegel, Y. Sorel","doi":"10.1109/DSD.2005.61","DOIUrl":"https://doi.org/10.1109/DSD.2005.61","url":null,"abstract":"This paper presents a new global MDA design methodology capable to bridge the gap between an abstract specification level and a heterogeneous architecture level while assisting real-time implementation. The P2I contribution is the result of a joint study on abstraction refinement methods and optimized mapping on architecture within a UML based design tools suite including SCADE/spl trade/ Suite for formal verifications and SynDEx for optimized distributed realtime implementation. The original points of this work are: i) a specification methodology that handles the control flow and the data flow representation, including efficient verifications, ii) a method for parallelism exploration based on abstract resources/performance estimation, iii) a HW/SW mapping approach that refines the specification into explicit HW configurations and the associated SW until executable distributed real-time code. The P2I framework shows how a cooperation of complementary methodologies and CAD tools associated with a relevant architecture can significantly improve the designer productivity, especially in the context of co-modelling for embedded design.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125753579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Co-simulation ofWireless Local Area Network Terminals with Protocol Software Implemented in SDL 在SDL中实现无线局域网终端与协议软件的联合仿真
8th Euromicro Conference on Digital System Design (DSD'05) Pub Date : 2005-08-30 DOI: 10.1109/DSD.2005.25
Petri Kukkala, Marko Hännikäinen, T. Hämäläinen
{"title":"Co-simulation ofWireless Local Area Network Terminals with Protocol Software Implemented in SDL","authors":"Petri Kukkala, Marko Hännikäinen, T. Hämäläinen","doi":"10.1109/DSD.2005.25","DOIUrl":"https://doi.org/10.1109/DSD.2005.25","url":null,"abstract":"This paper presents the verification of our WLAN terminal (TUTWLAN), with its medium access control protocol and test applications, using cycle-accurate hardware/ software co-simulation. The protocol software has been implemented using SDL and automatic C code generation. The hardware implementation of the terminal contains hardware accelerators for time-critical protocol functions. Full system co-simulations were used for both the functional verification and performance evaluation of a single TUTWLAN terminal as well as a network of terminals. With simulations, the performance bottlenecks were identified, and the results enable the implementing of the next generation TUTWLAN terminal as a single-chip.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134142892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
BIST technique for GALS systems GALS系统的BIST技术
8th Euromicro Conference on Digital System Design (DSD'05) Pub Date : 2005-08-30 DOI: 10.1109/DSD.2005.22
M. Krstic, E. Grass
{"title":"BIST technique for GALS systems","authors":"M. Krstic, E. Grass","doi":"10.1109/DSD.2005.22","DOIUrl":"https://doi.org/10.1109/DSD.2005.22","url":null,"abstract":"In this paper a test technique based on the built-in self-test (BIST) is proposed. Our BIST concept is based on hierarchical testing of the digital systems. The presented test scheme is optimized for globally asynchronous locally synchronous (GALS) systems. The BIST technique, described here, is implemented on a GALS baseband processor compliant to the IEEE 802.11a standard. Some results on the performance of our test solution are given. The GALS processor with embedded BIST was fabricated in IHP's 0.25 /spl mu/m CMOS technology and test results are presented.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130964947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Design of transport triggered architecture processors for wireless encryption 无线加密传输触发架构处理器的设计
8th Euromicro Conference on Digital System Design (DSD'05) Pub Date : 2005-08-30 DOI: 10.1109/DSD.2005.33
Panu Hämäläinen, J. Heikkinen, Marko Hännikäinen, T. Hämäläinen
{"title":"Design of transport triggered architecture processors for wireless encryption","authors":"Panu Hämäläinen, J. Heikkinen, Marko Hännikäinen, T. Hämäläinen","doi":"10.1109/DSD.2005.33","DOIUrl":"https://doi.org/10.1109/DSD.2005.33","url":null,"abstract":"Transport triggered architecture (TTA) offers a cost-effective trade-off between the size and performance of ASICs and the programmability of general-purpose processors. In this paper TTA processors for the RC4 and AES encryption algorithms of the new IEEE 802.11i WLAN security standard are designed. Special operations efficiently supporting the ciphers are developed. The TTA design flow is utilized for finding configurations with the best performance-size ratios. The size of the configuration supporting both the algorithms is 69.4 kgates and the throughput 100 Mb/s for RC4 and 68.5 Mb/s for AES at 100 MHz in the 0.13 /spl mu/m CMOS technology. Compared to commercial processors of the same wireless application domain, higher throughputs are achieved at significantly smaller area and lower clock speed, which also results in decreased energy consumption.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133427188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Decomposition of multi-output functions for CPLDs cpld的多输出功能分解
8th Euromicro Conference on Digital System Design (DSD'05) Pub Date : 2005-08-30 DOI: 10.1109/DSD.2005.29
D. Kania, A. Milik, Józef Kulisz
{"title":"Decomposition of multi-output functions for CPLDs","authors":"D. Kania, A. Milik, Józef Kulisz","doi":"10.1109/DSD.2005.29","DOIUrl":"https://doi.org/10.1109/DSD.2005.29","url":null,"abstract":"A paper presents decomposition method dedicated for PAL based CPLDs. Non-standard usage of decomposition, that leads to minimization of area in implemented circuit and reduction of used logic blocks in programmable structure is the aim of proposed method. Each decomposition step (bound set selection, graph colouring, column pattern coding, etc) is oriented for implementation in PAL-based structure that characterized by PAL-based logic block. Proposed decomposition method is an extension of classical approach commonly thought to be sufficiently efficient. Experiments that were carried out on typical benchmarks show significant area reduction.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131312415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An advanced minimization technique for multiple valued multiple output logic expressions using LUT and realization using current mode CMOS 利用LUT实现多值多输出逻辑表达式的先进最小化技术，并利用电流模CMOS实现
8th Euromicro Conference on Digital System Design (DSD'05) Pub Date : 2005-08-30 DOI: 10.1109/DSD.2005.13
Md. Sumon Shahriar, A. Mustafa, Chowdhury Farhan Ahmed, Abu Ahmed Ferdaus, A. N. M. Zaheduzzaman, Shahed Anwar, H. Babu
{"title":"An advanced minimization technique for multiple valued multiple output logic expressions using LUT and realization using current mode CMOS","authors":"Md. Sumon Shahriar, A. Mustafa, Chowdhury Farhan Ahmed, Abu Ahmed Ferdaus, A. N. M. Zaheduzzaman, Shahed Anwar, H. Babu","doi":"10.1109/DSD.2005.13","DOIUrl":"https://doi.org/10.1109/DSD.2005.13","url":null,"abstract":"We proposed an advanced minimization method for multiple valued multiple output functions in this paper. We extracted the shared sub functions with a proposed heuristic method to pair the functions. New minimization approach for multiple valued functions has also been proposed where we used Kleenean coefficients and we used LUT to reduce the complexity as well. Our minimization method reduces the number of implicants significantly. The realization of the minimized circuits has also been shown using current mode CMOS.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"217 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122483873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A new architecture for fast arithmetic coding in H.264 advanced video coder H.264高级视频编码器中快速算术编码的新架构
8th Euromicro Conference on Digital System Design (DSD'05) Pub Date : 2005-08-30 DOI: 10.1109/DSD.2005.9
R. Osorio, J. Bruguera
{"title":"A new architecture for fast arithmetic coding in H.264 advanced video coder","authors":"R. Osorio, J. Bruguera","doi":"10.1109/DSD.2005.9","DOIUrl":"https://doi.org/10.1109/DSD.2005.9","url":null,"abstract":"In this work, a new architecture for binary arithmetic coding is presented in the context of the new AVC/H.264 standard for video coding. Among the new technologies included in AVC/H.264 a context adaptive binary arithmetic coder (CABAC) is used that outperforms the baseline entropy coder in a significant manner. In this work we justify the need for a new architecture that implements the unique characteristics of CABAC that are not found in other implementations of arithmetic coding. We show that a fast architecture is needed that combines short cycle time and application-aware scheduling in order to accomplish with the high computational demands. A number of optimizations are introduced that allow processing several symbols per cycle and reduce data binarization overhead. Implementation results are shown for a Virtex-II FPGA and the main conclusions are presented.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122649601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
An effective framework for enabling the reuse of external soft IP 实现外部软IP复用的有效框架
8th Euromicro Conference on Digital System Design (DSD'05) Pub Date : 2005-08-30 DOI: 10.1109/DSD.2005.16
Soujanna Sarkar, G. SubashChandar
{"title":"An effective framework for enabling the reuse of external soft IP","authors":"Soujanna Sarkar, G. SubashChandar","doi":"10.1109/DSD.2005.16","DOIUrl":"https://doi.org/10.1109/DSD.2005.16","url":null,"abstract":"Intellectual property (IP) reuse is essential for meeting the challenges of system-on-a-chip (SoC) design productivity improvement, design quality and meeting time-to-market goals. Recent trend in the design of complex SoC is doing a joint development with the customer, where it is required to integrate some of their IPs. In such a scenario, the usual paradigm followed for reuse has to be enhanced beyond the state of the art to meet the design goals. This paper describes the reuse framework that has been successfully applied during such a joint development program. The methodology consists of imposing a specified degree of compliance for internal checklists comprising of code quality, design quality, verification quality, and testability checks, and aligning on the goals for design verification and test coverage. Customized enhancements to the IPs to meet the SoC design goals are presented.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128535717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Throughput of streaming applications running on a multiprocessor architecture 在多处理器架构上运行的流应用程序的吞吐量
8th Euromicro Conference on Digital System Design (DSD'05) Pub Date : 2005-08-30 DOI: 10.1109/DSD.2005.73
N. Kavaldjiev, G. Smit, P. Jansen
{"title":"Throughput of streaming applications running on a multiprocessor architecture","authors":"N. Kavaldjiev, G. Smit, P. Jansen","doi":"10.1109/DSD.2005.73","DOIUrl":"https://doi.org/10.1109/DSD.2005.73","url":null,"abstract":"In this paper we study the timing behaviour of streaming applications running on a multiprocessor architecture. Dependencies are derived between the application throughput and the timing characteristics of the processors and communication. Four different processor organizations that strongly influenced the results are considered and compared.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128638492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
On LUT cascade realizations of FIR filters FIR滤波器的LUT级联实现
8th Euromicro Conference on Digital System Design (DSD'05) Pub Date : 2005-08-30 DOI: 10.1109/DSD.2005.82
Tsutomu Sasao, Y. Iguchi, Takahiro Suzuki
{"title":"On LUT cascade realizations of FIR filters","authors":"Tsutomu Sasao, Y. Iguchi, Takahiro Suzuki","doi":"10.1109/DSD.2005.82","DOIUrl":"https://doi.org/10.1109/DSD.2005.82","url":null,"abstract":"This paper first defines the n-input q-output WS function, as a mathematical model of the combinational part of the distributed arithmetic of a finite impulse response (FIR) filter. Then, it shows a method to realize the WS function by an LUT cascade with k-input q-output cells. Furthermore, it 1) shows that LUT cascade realizations require much smaller memory than the single ROM realizations; 2) presents new design method for a WS function by arithmetic decomposition, and 3) shows design results of FIR filters using FPGAs with embedded memories.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125428687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
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