{"title":"GALS系统的BIST技术","authors":"M. Krstic, E. Grass","doi":"10.1109/DSD.2005.22","DOIUrl":null,"url":null,"abstract":"In this paper a test technique based on the built-in self-test (BIST) is proposed. Our BIST concept is based on hierarchical testing of the digital systems. The presented test scheme is optimized for globally asynchronous locally synchronous (GALS) systems. The BIST technique, described here, is implemented on a GALS baseband processor compliant to the IEEE 802.11a standard. Some results on the performance of our test solution are given. The GALS processor with embedded BIST was fabricated in IHP's 0.25 /spl mu/m CMOS technology and test results are presented.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"BIST technique for GALS systems\",\"authors\":\"M. Krstic, E. Grass\",\"doi\":\"10.1109/DSD.2005.22\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper a test technique based on the built-in self-test (BIST) is proposed. Our BIST concept is based on hierarchical testing of the digital systems. The presented test scheme is optimized for globally asynchronous locally synchronous (GALS) systems. The BIST technique, described here, is implemented on a GALS baseband processor compliant to the IEEE 802.11a standard. Some results on the performance of our test solution are given. The GALS processor with embedded BIST was fabricated in IHP's 0.25 /spl mu/m CMOS technology and test results are presented.\",\"PeriodicalId\":119054,\"journal\":{\"name\":\"8th Euromicro Conference on Digital System Design (DSD'05)\",\"volume\":\"14 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-08-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"8th Euromicro Conference on Digital System Design (DSD'05)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DSD.2005.22\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"8th Euromicro Conference on Digital System Design (DSD'05)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DSD.2005.22","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11
摘要
提出了一种基于内置自检(BIST)的测试技术。我们的BIST概念是基于数字系统的分层测试。提出的测试方案针对全局异步局部同步(GALS)系统进行了优化。这里描述的BIST技术是在符合IEEE 802.11a标准的GALS基带处理器上实现的。给出了测试方案的一些性能结果。采用IHP的0.25 /spl μ m CMOS工艺制作了嵌入式BIST的GALS处理器，并给出了测试结果。
In this paper a test technique based on the built-in self-test (BIST) is proposed. Our BIST concept is based on hierarchical testing of the digital systems. The presented test scheme is optimized for globally asynchronous locally synchronous (GALS) systems. The BIST technique, described here, is implemented on a GALS baseband processor compliant to the IEEE 802.11a standard. Some results on the performance of our test solution are given. The GALS processor with embedded BIST was fabricated in IHP's 0.25 /spl mu/m CMOS technology and test results are presented.
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