A new architecture for fast arithmetic coding in H.264 advanced video coder

R. Osorio, J. Bruguera
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引用次数: 28

Abstract

In this work, a new architecture for binary arithmetic coding is presented in the context of the new AVC/H.264 standard for video coding. Among the new technologies included in AVC/H.264 a context adaptive binary arithmetic coder (CABAC) is used that outperforms the baseline entropy coder in a significant manner. In this work we justify the need for a new architecture that implements the unique characteristics of CABAC that are not found in other implementations of arithmetic coding. We show that a fast architecture is needed that combines short cycle time and application-aware scheduling in order to accomplish with the high computational demands. A number of optimizations are introduced that allow processing several symbols per cycle and reduce data binarization overhead. Implementation results are shown for a Virtex-II FPGA and the main conclusions are presented.
H.264高级视频编码器中快速算术编码的新架构
本文提出了一种新的基于AVC/H的二进制算术编码体系结构。264视频编码标准。AVC/H中包含的新技术。264使用上下文自适应二进制算术编码器(CABAC),其以显著的方式优于基线熵编码器。在这项工作中,我们证明需要一种新的体系结构来实现CABAC的独特特性,而这些特性在其他算术编码实现中是找不到的。为了满足高计算需求,需要一种结合短周期时间和应用程序感知调度的快速架构。引入了许多优化,允许每个周期处理多个符号并减少数据二值化开销。给出了Virtex-II FPGA的实现结果,并给出了主要结论。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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