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8th Euromicro Conference on Digital System Design (DSD'05)最新文献

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High-level synthesis in latency insensitive system methodology 延迟不敏感系统方法学的高级综合
8th Euromicro Conference on Digital System Design (DSD'05) Pub Date : 2005-08-30 DOI: 10.1109/DSD.2005.47
P. Bomel, N. Abdelli, E. Martin, A. Fouilliart, E. Boutillon, P. Kajfasz
{"title":"High-level synthesis in latency insensitive system methodology","authors":"P. Bomel, N. Abdelli, E. Martin, A. Fouilliart, E. Boutillon, P. Kajfasz","doi":"10.1109/DSD.2005.47","DOIUrl":"https://doi.org/10.1109/DSD.2005.47","url":null,"abstract":"This paper presents our contribution in terms of synchronization processor to a SoC design methodology based on the theory of the latency insensitive systems (US). This methodology 1) promotes pre-developed IPs intensive reuse, 2) segments inter-IPs interconnects with relay stations to break critical paths and 3) brings robustness to data stream irregularities to IPs by encapsulation into a synchronization wrapper. Our contribution consists of IP encapsulation into a new wrapper model containing a synchronization processor, which speed and area are optimized and synthesizability guaranteed. The main benefit of our approach is to preserve the local IP performances when encapsulating them. This approach is part of the RNRT ALIPTA project which targets design automation of intensive digital signal processing systems with GAUT, a high-level synthesis tool.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115397040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Power-constrained hybrid BIST test scheduling in an abort-on-first-fail test environment 一失败即中止测试环境下功率受限的混合型BIST测试调度
8th Euromicro Conference on Digital System Design (DSD'05) Pub Date : 2005-08-30 DOI: 10.1109/DSD.2005.63
Zhiyuan He, G. Jervan, Zebo Peng, P. Eles
{"title":"Power-constrained hybrid BIST test scheduling in an abort-on-first-fail test environment","authors":"Zhiyuan He, G. Jervan, Zebo Peng, P. Eles","doi":"10.1109/DSD.2005.63","DOIUrl":"https://doi.org/10.1109/DSD.2005.63","url":null,"abstract":"This paper presents a method for power-constrained system-on-chip test scheduling in an abort-on-first-fail environment where the test is terminated as soon as a fault is detected. We employ the defect probabilities of individual cores to guide the scheduling, such that the expected total test time is minimized and the peak power constraint is satisfied. Based on a hybrid BIST architecture where a combination of deterministic and pseudorandom test sequences is used, the power-constrained test scheduling problem can be formulated as an extension of the two-dimensional rectangular packing problem and a heuristic has been proposed to calculate the near optimal order of different test sequences. The method is also generalized for both test-per-clock and test-per-scan approaches. Experimental results have shown that the proposed heuristic is efficient to find a near optimal test schedule with a low computation overhead.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115420294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Characterization of wavelet-based image coding systems for algorithmic fault detection 基于小波的图像编码系统故障检测算法
8th Euromicro Conference on Digital System Design (DSD'05) Pub Date : 2005-08-30 DOI: 10.1109/DSD.2005.24
L. Costas, J. Rodríguez-Andina
{"title":"Characterization of wavelet-based image coding systems for algorithmic fault detection","authors":"L. Costas, J. Rodríguez-Andina","doi":"10.1109/DSD.2005.24","DOIUrl":"https://doi.org/10.1109/DSD.2005.24","url":null,"abstract":"This paper presents a methodology for characterizing the behaviour of wavelet-based image coding systems in the presence of faults. This is a previous step in the development of efficient concurrent error detection techniques for such systems. The faulty behaviour of complex signal processing systems is better described at the algorithmic level (i.e., checking the accomplishment of a given functional property by large blocks of data) rather than using the ''classical'' approach at the structural (i.e., building block) level. Therefore, the issues related to algorithmic fault detection are addressed. Two different platforms for error characterization are presented and their main characteristics are discussed. Experimental results are presented that prove the suitability of the proposed methodology for the target application.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123459439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Exploring graphics processor performance for general purpose applications 探索通用应用程序的图形处理器性能
8th Euromicro Conference on Digital System Design (DSD'05) Pub Date : 2005-08-30 DOI: 10.1109/DSD.2005.40
P. Trancoso, Maria Charalambous
{"title":"Exploring graphics processor performance for general purpose applications","authors":"P. Trancoso, Maria Charalambous","doi":"10.1109/DSD.2005.40","DOIUrl":"https://doi.org/10.1109/DSD.2005.40","url":null,"abstract":"Graphics processors are designed to perform many floating-point operations per second. Consequently, they are an attractive architecture for high-performance computing at a low cost. Nevertheless, it is still not very clear how to exploit all their potential for general-purpose applications. In this work we present a comprehensive study of the performance of an application executing on the GPU. In addition, we analyze the possibility of using the graphics card to extend the life-time of a computer system. In our experiments we compare the execution on a mid-class GPU (NVIDIA GeForce FX 5700LE) with a high-end CPU (Pentium 4 3.2 GHz). The results show that to achieve high speedup with the GPU you need to: (1) format the vectors into two-dimensional arrays; (2) process large data arrays; and (3) perform a considerable amount of operations per data element. Finally, we study the performance when upgrading a low-end system by simply adding a GPU. This solution is cheaper, results in smaller power consumption and achieves higher speedup (8.1x versus 1.3x) than a full upgrade to a new high-end system.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129809761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
Run-time adaptive resources allocation and balancing on nanoprocessors arrays 纳米处理器阵列上的运行时自适应资源分配和平衡
8th Euromicro Conference on Digital System Design (DSD'05) Pub Date : 2005-08-30 DOI: 10.1109/DSD.2005.70
D. Pani, G. Passino, L. Raffo
{"title":"Run-time adaptive resources allocation and balancing on nanoprocessors arrays","authors":"D. Pani, G. Passino, L. Raffo","doi":"10.1109/DSD.2005.70","DOIUrl":"https://doi.org/10.1109/DSD.2005.70","url":null,"abstract":"Modern processor architectures try to exploit the different kind of parallelism that may be found even in general purpose applications. In this paper we present a new architecture based on an array of nanoprocessors that parallely and cooperatively support both Thread and Instruction level parallelism. A such architecture doesn't explicitly require any particular programming techniques since it has been developed to deal with standard sequential programs. Preliminary results on a model of the architecture show the feasibility of the proposed approach.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"207 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121287195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A low-power FIR filter using combined residue and radix-2 signed-digit representation 一种低功耗FIR滤波器，采用组合残数和基数2符号数表示
8th Euromicro Conference on Digital System Design (DSD'05) Pub Date : 2005-08-30 DOI: 10.1109/DSD.2005.8
Andreas Lindahl, L. Bengtsson
{"title":"A low-power FIR filter using combined residue and radix-2 signed-digit representation","authors":"Andreas Lindahl, L. Bengtsson","doi":"10.1109/DSD.2005.8","DOIUrl":"https://doi.org/10.1109/DSD.2005.8","url":null,"abstract":"This paper presents a FIR filter combining residue (RNS) and radix-2 signed digit (SD) representation. RNS offers parallelization of the computations and SD carry-free additions. The moduli set {2/sup n/-1, 2/sup n/, 2/sup n/+1} is used reducing the complexity of the RNS arithmetic units. The evaluated filters have 8, 12 and 16 taps, binary word lengths between 16 and 64 bits, and have been synthesized using a UMC 0.13 /spl mu/m CMOS cell library with 8 metal layers. Power, delay, and area comparisons are made with equivalent 2's complement designs. The area-delay and area-delay-power products shows that reduction in both power and area at the same filter throughput can be expected.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122782741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
An educational environment for digital testing: hardware, tools, and Web-based runtime platform 用于数字测试的教育环境:硬件、工具和基于web的运行时平台
8th Euromicro Conference on Digital System Design (DSD'05) Pub Date : 2005-08-30 DOI: 10.1109/DSD.2005.15
A. Jutman, J. Raik, R. Ubar, V. Vislogubov
{"title":"An educational environment for digital testing: hardware, tools, and Web-based runtime platform","authors":"A. Jutman, J. Raik, R. Ubar, V. Vislogubov","doi":"10.1109/DSD.2005.15","DOIUrl":"https://doi.org/10.1109/DSD.2005.15","url":null,"abstract":"We describe a new e-learning environment and a runtime platform for educational tools on digital system testing and design for testability. This environment is being developed in Tallinn University of Technology and consists of several functional layers. The first one is the hardware component used for illustration of various physical phenomena appearing in defected circuits. In many cases such phenomena are hard to illustrate by software simulation or by any other means, which makes the usage of such a hardware component unavoidable. The second component is a set of university tools covering a large scope of topics in basics of testing, diagnosis, and BIST. The tools represent an efficient alternative to hard-to-learn and expensive commercial CAD systems. The wrapper to these two components is a cross-platform Web interface that represents a server-based solution for using all the available tools and the hardware over Internet. The whole platform is an extendable server-based low-cost solution, which is easy to set-up and use. The learning environment is complemented by laboratory work scenarios and teaching materials that also available in the Web.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126277917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Delay testability properties of circuits implementing threshold and symmetric functions 实现阈值和对称函数的电路的延迟可测试性
8th Euromicro Conference on Digital System Design (DSD'05) Pub Date : 2005-08-30 DOI: 10.1109/DSD.2005.31
Piotr Patronik
{"title":"Delay testability properties of circuits implementing threshold and symmetric functions","authors":"Piotr Patronik","doi":"10.1109/DSD.2005.31","DOIUrl":"https://doi.org/10.1109/DSD.2005.31","url":null,"abstract":"In this paper, we present a general method for proving robust delay testability of multi-output threshold circuit. We prove that robust delay testability of some class of multi-output threshold circuits depends only on the set of well-defined properties of the merging circuits. We also prove the robust delay testability properties of two existing design methods of multi-output threshold circuits: one presented by Reddy and the improved one by Rahaman et al., (2003).","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126701868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Yield-aware floorplanning Yield-aware平面布置图
8th Euromicro Conference on Digital System Design (DSD'05) Pub Date : 2005-08-30 DOI: 10.1109/DSD.2005.80
Zhaojun Wo, I. Koren, M. Ciesielski
{"title":"Yield-aware floorplanning","authors":"Zhaojun Wo, I. Koren, M. Ciesielski","doi":"10.1109/DSD.2005.80","DOIUrl":"https://doi.org/10.1109/DSD.2005.80","url":null,"abstract":"Yield is normally ignored during the floorplanning stage. Recently, it has been shown that floorplanning can affect the yield with the increased sizes of chips. With the \"medium-area clustering\" model, yield can be evaluated during the floorplanning stage. Therefore, it's straightforward to incorporate yield in modern floorplanners. However, conventional simulate-annealing (SA) based moves are only designed for the combination of the area and/or the wire length minimizations. In this paper, we proposed a heuristic scheme of \"moves\" directly targeting on the yield improvement. The experimental results show a great yield improvement with little penalty for the area and/or the total wire length.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130665055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Automatic design of binary and multiple-valued logic gates on RTD series RTD系列上二进制和多值逻辑门的自动设计
8th Euromicro Conference on Digital System Design (DSD'05) Pub Date : 2005-08-30 DOI: 10.1109/DSD.2005.21
Krzysztof S. Berezowski, S. Vrudhula
{"title":"Automatic design of binary and multiple-valued logic gates on RTD series","authors":"Krzysztof S. Berezowski, S. Vrudhula","doi":"10.1109/DSD.2005.21","DOIUrl":"https://doi.org/10.1109/DSD.2005.21","url":null,"abstract":"In this paper, we contribute to the binary and multiple-valued applications of resonant tunneling devices (RTDs). We propose a method of systematic design of physical parameters of RTD based logic. From the abstraction of their behavior, we model the design space as a handful of systems of linear inequalities generated for a given circuit topology and an arbitrary logic function. Any valid solution reflects the physical parameters assignment that implements the function given. We solve these systems using off-the-shelf optimization tool and verify the results using SystemC based RTD circuit model. Our simulations confirm that the numerical solutions are valid parameter assignments.","PeriodicalId":119054,"journal":{"name":"8th Euromicro Conference on Digital System Design (DSD'05)","volume":"231 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134390204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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