Delay testability properties of circuits implementing threshold and symmetric functions

Abstract

In this paper, we present a general method for proving robust delay testability of multi-output threshold circuit. We prove that robust delay testability of some class of multi-output threshold circuits depends only on the set of well-defined properties of the merging circuits. We also prove the robust delay testability properties of two existing design methods of multi-output threshold circuits: one presented by Reddy and the improved one by Rahaman et al., (2003).