2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)最新文献

Embedded tutorial — Compilation techniques for CGRAs: Exploring all parallelization approaches 嵌入式教程- CGRAs的编译技术:探索所有并行化方法

2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2010-10-24 DOI: 10.1145/1878961.1878995

T. Aa, P. Raghavan, S. Mahlke, B. D. Sutter, Aviral Shrivastava, Frank Hannig

引用次数: 2

Modeling and analyzing real-time multiprocessor systems 建模和分析实时多处理器系统

2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2010-10-24 DOI: 10.1145/1878961.1879019

M. Wiggers, L. Thiele, Edward A. Lee, S. Schliecker, M. Bekooij

引用次数: 2

Towards a synthesis semantics for SystemC channels 迈向SystemC通道的综合语义

2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2010-10-24 DOI: 10.1145/1878961.1878990

Kim Grüttner, Henning Kleen, F. Oppenheimer, A. Rettberg, W. Nebel

引用次数: 9

From ESL 2010 to ESL 2015 从ESL 2010到ESL 2015

2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2010-10-24 DOI: 10.1145/1878961.1878973

Tor E. Jeremiassen, Tim Kogel, A. Takach, G. Martin, A. Donlin, K. Chatha

引用次数: 1

A greedy buffer allocation algorithm for power-aware communication in body sensor networks 身体传感器网络中功率感知通信的贪婪缓冲区分配算法

2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2010-10-24 DOI: 10.1145/1878961.1878998

Hassan Ghasemzadeh, R. Jafari

引用次数: 5

OE+IOE: A novel turn model based fault tolerant routing scheme for networks-on-chip OE+IOE:一种基于回合模型的片上网络容错路由方案

2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2010-10-24 DOI: 10.1145/1878961.1878979

S. Pasricha, Yong Zou, D. Connors, H. Siegel

{"title":"OE+IOE: A novel turn model based fault tolerant routing scheme for networks-on-chip","authors":"S. Pasricha, Yong Zou, D. Connors, H. Siegel","doi":"10.1145/1878961.1878979","DOIUrl":"https://doi.org/10.1145/1878961.1878979","url":null,"abstract":"Network-on-chip (NoC) communication architectures are increasingly being used today to interconnect cores on chip multiprocessors (CMPs). Permanent faults in NoCs due to fabrication challenges in ultra deep submicron (UDSM) technology nodes and due to wearout have led to an increased emphasis on fault tolerant design techniques. To ensure fault tolerant communication in NoCs, several fault tolerant routing algorithms have been proposed in recent years with the goal of routing flits around faults. A majority of these algorithms are based on the turn model approach due to its simplicity and inherent freedom from deadlock. However, existing turn model based fault tolerant routing algorithms are either too restrictive in the choice of paths that flits can traverse, or are tailored to work efficiently only on very specific fault distribution patterns. In this paper, we propose a novel low overhead fault tolerant routing scheme that combines the odd-even (OE) and inverted odd-even (IOE) turn models to achieve much better fault tolerance than traditional turn model based schemes. The proposed scheme uses replication opportunistically to optimize the balance between energy overhead and arrival rate. Our experimental results indicate that the proposed OE+IOE routing scheme provides better fault tolerance than existing turn model, N-random walk, and dual virtual channel based routing schemes that have been proposed in literature.","PeriodicalId":118816,"journal":{"name":"2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115056394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 36

Worst-case performance analysis of Synchronous Dataflow scenarios 同步数据流场景最坏情况性能分析

2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2010-10-24 DOI: 10.1145/1878961.1878985

M. Geilen, S. Stuijk

{"title":"Worst-case performance analysis of Synchronous Dataflow scenarios","authors":"M. Geilen, S. Stuijk","doi":"10.1145/1878961.1878985","DOIUrl":"https://doi.org/10.1145/1878961.1878985","url":null,"abstract":"Synchronous Dataflow (SDF) is a powerful analysis tool for regular, cyclic, parallel task graphs. The behaviour of SDF graphs however is static and therefore not always able to accurately capture the behaviour of modern, dynamic dataflow applications, such as embedded multimedia codecs. An approach to tackle this limitation is by means of scenarios. In this paper we introduce a technique and a tool to automatically analyse a scenario-aware dataflow model for its worst-case performance. A system is specified as a collection of SDF graphs representing individual scenarios of behaviour and a finite state machine that specifies the possible orders of scenario occurrences. This combination accurately captures more dynamic applications and this way provides tighter results than an existing analysis based on a conservative static dataflow model, which is too pessimistic, while looking only at the `worst-case' individual scenario, without considering scenario transitions, can be too optimistic. We introduce a formal semantics of the model, in terms of (max; +) linear system-theory and in particular (max; +) automata. Leveraging existing results and algorithms from this domain, we give throughput analysis and state space generation algorithms for worst-case performance analysis. The method is implemented in a tool and the effectiveness of the approach is experimentally evaluated.","PeriodicalId":118816,"journal":{"name":"2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)","volume":"1984 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130621857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 103

FEMU: A firmware-based emulation framework for SoC verification FEMU:用于SoC验证的基于固件的仿真框架

2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2010-10-24 DOI: 10.1145/1878961.1879007

Hao Li, Dong Tong, Kan Huang, Xu Cheng

{"title":"FEMU: A firmware-based emulation framework for SoC verification","authors":"Hao Li, Dong Tong, Kan Huang, Xu Cheng","doi":"10.1145/1878961.1879007","DOIUrl":"https://doi.org/10.1145/1878961.1879007","url":null,"abstract":"Full-system emulation on FPGA(Field-Programmable Gate Array) with real-world workloads can enhance the confidence of SoC(System-on-Chip) design. However, since FPGA emulation requires complete implementation of key modules and provides weak visibility, it is time-consuming. This paper proposes FEMU, a hybrid firmware/hardware emulation framework for SoC verification. The core of FEMU is implemented by transplanting QEMU, a full-system emulator, from OS level to BIOS level, so we can directly emulate devices upon hardware. Moreover, FEMU provides programming interfaces to simplify device modeling in firmware. Based on an auxiliary set of hardware modules, FEMU allows hybrid full-system emulation with the combination of real hardware and emulated firmware model. Therefore, FEMU can facilitate full-system emulation in three aspects. First, FEMU enables full-system emulation with the minimum hardware implementation, so the DUT (Design Under Test) module can be verified under target application as early as possible. Second, by comparing the execution traces generated using real hardware and emulated firmware model, respectively, FEMU helps locate and fix bugs occurred in the full-system emulation. Third, by replacing un-verified hardware modules with emulated firmware models, FEMU helps isolating design issues in multiple modules. In a practical SoC project, FEMU helped us identify several design issues in full-system emulation. In addition, the evaluation results show that the emulation speed of FEMU is comparable with QEMU after transplantation.","PeriodicalId":118816,"journal":{"name":"2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128592229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

A case for lifetime-aware task mapping in embedded chip multiprocessors 嵌入式芯片多处理器中生命周期感知任务映射的一个案例

2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2010-10-24 DOI: 10.1145/1878961.1878987

Adam S. Hartman, D. E. Thomas, B. Meyer

{"title":"A case for lifetime-aware task mapping in embedded chip multiprocessors","authors":"Adam S. Hartman, D. E. Thomas, B. Meyer","doi":"10.1145/1878961.1878987","DOIUrl":"https://doi.org/10.1145/1878961.1878987","url":null,"abstract":"Temperature-aware design is emerging as a popular approach to addressing a variety of challenges, including system lifetime. In the case of task mapping, temperature-aware approaches indeed improve lifetime due to lifetime's strong dependence on tempera-ture. However, temperature-aware design neglects several important factors that also influence lifetime: (a) physical parameters such as supply voltage and current density, as well as (b) application and architecture characteristics that affect what failures are survivable. Only lifetime-aware task mapping can expose the relationship between physical parameters, component failure, and system lifetime, and therefore find lifetime-optimal mappings. To address this need, we have developed a new lifetime-aware task mapping technique based on ant colony optimization (ACO). Our technique produces task mappings resulting in lifetimes with-in 17.9% of the observed optimal results on average, outperform-ing a lifetime-agnostic task mapping approach by an average of 32.3%. We also observed that the lifetimes resulting from task mappings within 1% of the best maximum system temperature vary by an average of 20.1% while the lifetimes resulting from task mappings within 1% of the best average system temperature vary by an average of 32.6%. Our observations lead us to conclude that one cannot depend on temperature-aware task mapping when system lifetime is a design constraint, but one may depend on lifetime-aware task mapping when one or both of lifetime and temperature are design constraints.","PeriodicalId":118816,"journal":{"name":"2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121419311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 40

Verification of dynamically reconfigurable embedded systems by model transformation rules 基于模型转换规则的动态可重构嵌入式系统验证

2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) Pub Date : 2010-10-24 DOI: 10.1145/1878961.1878969

F. Madlener, J. Weingart, S. Huss

引用次数: 12