Proceedings of the second international conference on Architectual support for programming languages and operating systems最新文献_第2页

Coherency for multiprocessor virtual address caches 多处理器虚拟地址缓存的一致性

Proceedings of the second international conference on Architectual support for programming languages and operating systems Pub Date : 1987-10-01 DOI: 10.1145/36206.36186

J. Goodman

引用次数: 90

Firefly: a multiprocessor workstation 萤火虫:一个多处理器工作站

Proceedings of the second international conference on Architectual support for programming languages and operating systems Pub Date : 1987-10-01 DOI: 10.1145/36206.36199

C. Thacker, L. Stewart, E. Satterthwaite

{"title":"Firefly: a multiprocessor workstation","authors":"C. Thacker, L. Stewart, E. Satterthwaite","doi":"10.1145/36206.36199","DOIUrl":"https://doi.org/10.1145/36206.36199","url":null,"abstract":"Firefly is a shared-memory multiprocessor workstation that contains from one to seven MicroVAX 78032 processors, each with a floating point unit and a sixteen kilobyte cache. The caches are coherent, so that all processors see a consistent view of main memory. A system may contain from four to sixteen megabytes of storage. Input-output is done via a standard DEC QBus. Input-output devices are an Ethernet controller, fixed disks, and a monochrome 1024 x 768 display with keyboard and mouse. Optional hardware includes a high resolution color display and a controller for high capacity disks. Figure 1 is a system block diagram.The Firefly runs a software system that emulates the Ultrix system call interface. It also supports medium- and coarse-grained multiprocessing through multiple threads of control in a single address space. Communications are implemented uniformly through the use of remote procedure calls.This paper describes the goals, architecture, implementation and performance analysis of the Firefly. It then presents some measurements of hardware performance, and discusses the degree to which SRC has been successful in producing software to take advantage of multiprocessing.","PeriodicalId":117067,"journal":{"name":"Proceedings of the second international conference on Architectual support for programming languages and operating systems","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129313826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 286

The Mahler experience: using an intermediate language as the machine description 马勒经验:使用中间语言作为机器描述

Proceedings of the second international conference on Architectual support for programming languages and operating systems Pub Date : 1987-10-01 DOI: 10.1145/36206.36190

D. W. Wall, M. L. Powell

引用次数: 57

Hardware architectures for programming languages and programming languages for hardware architectures 用于编程语言的硬件架构和用于硬件架构的编程语言

Proceedings of the second international conference on Architectual support for programming languages and operating systems Pub Date : 1987-10-01 DOI: 10.1145/36206.36178

N. Wirth

引用次数: 11

Tags and type checking in LISP: hardware and software approaches LISP中的标记和类型检查:硬件和软件方法

Proceedings of the second international conference on Architectual support for programming languages and operating systems Pub Date : 1987-10-01 DOI: 10.1145/36206.36183

P. Steenkiste, J. Hennessy

{"title":"Tags and type checking in LISP: hardware and software approaches","authors":"P. Steenkiste, J. Hennessy","doi":"10.1145/36206.36183","DOIUrl":"https://doi.org/10.1145/36206.36183","url":null,"abstract":"One of the major factors that distinguishes LISP from many other languages (Pascal, C, Fortran, etc.) is the need for run-time type checking. Run-time type checking is implemented by adding to each data object a tag that encodes type information. Tags must be compared for type compatibility, removed when using the data, and inserted when new data items are created. This tag manipulation, together with other work related to dynamic type checking and generic operations, constitutes a significant component of the execution time of LISP programs. This has led both to the development of LISP machines that support tag checking in hardware and to the avoidance of type checking by users running on stock hardware. To understand the role and necessity of special-purpose hardware for tag handling, we first measure the cost of type checking operations for a group of LISP programs. We then examine hardware and software implementations of tag operations and estimate the cost of tag handling with the different tag implementation schemes. The data shows that minimal levels of support provide most of the benefits, and that tag operations can be relatively inexpensive, even when no special hardware support is present.","PeriodicalId":117067,"journal":{"name":"Proceedings of the second international conference on Architectual support for programming languages and operating systems","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124553831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 49

Cheap hardware support for software debugging and profiling 对软件调试和分析的廉价硬件支持

Proceedings of the second international conference on Architectual support for programming languages and operating systems Pub Date : 1987-10-01 DOI: 10.1145/36177.36187

T. Cargill, B. Locanthi

引用次数: 48

Integer multiplication and division on the HP precision architecture 整数乘法和除法在HP精密架构上

Proceedings of the second international conference on Architectual support for programming languages and operating systems Pub Date : 1987-10-01 DOI: 10.1145/36206.36189

D. Magenheimer, Liz Peters, Karl Pettis, D. Zuras

引用次数: 54

RISCs vs. CISCs for Prolog: a case study RISCs vs. CISCs for Prolog:一个案例研究

Proceedings of the second international conference on Architectual support for programming languages and operating systems Pub Date : 1987-10-01 DOI: 10.1145/36206.36196

G. Borriello, A. Cherenson, P. Danzig, M. Nelson

{"title":"RISCs vs. CISCs for Prolog: a case study","authors":"G. Borriello, A. Cherenson, P. Danzig, M. Nelson","doi":"10.1145/36206.36196","DOIUrl":"https://doi.org/10.1145/36206.36196","url":null,"abstract":"This paper compares the performance of executing compiled Prolog code on two different architectures under development at U. C. Berkeley. The first is the PLM, a special-purpose CISC architecture intended as a coprocessor for a host machine. The second is SPUR, a general-purpose RISC architecture that supports tagged data. Fourteen standard benchmark programs were run on both the PLM and SPUR simulators. The compiled code for SPUR was obtained by simple macro-expansion of PLM code generated by the PLM Prolog compiler. The two implementations are compared with regard to static and dynamic program size, execution speed, and memory system performance. On average, the macrocoded SPUR implementation has a static code size 14 times larger than the PLM, executes 16 times more instructions, yet requires only 2.3 times the number of machine cycles (or has the performance of 0.43 PLMs). When memory system performance is taken into account, SPUR is equivalent to 0.29 PLMs. Optimizations of the macro-expanded code and minor architectural changes to SPUR would increase this ratio to 0.53, or 0.60 for the largest benchmarks. Thus a tagged RISC architecture can execute Prolog at least half as fast as a special-purpose CISC architecture for Prolog.","PeriodicalId":117067,"journal":{"name":"Proceedings of the second international conference on Architectual support for programming languages and operating systems","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115316621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 22

Performance and architectural evaluation of the PSI machine PSI机器的性能和架构评估

Proceedings of the second international conference on Architectual support for programming languages and operating systems Pub Date : 1987-10-01 DOI: 10.1145/36206.36195

K. Taki, K. Nakajima, H. Nakashima, Morihiro Ikeda

{"title":"Performance and architectural evaluation of the PSI machine","authors":"K. Taki, K. Nakajima, H. Nakashima, Morihiro Ikeda","doi":"10.1145/36206.36195","DOIUrl":"https://doi.org/10.1145/36206.36195","url":null,"abstract":"We evaluated a Prolog machine PSI (Personal Sequential Inference machine) for the purpose of improving and redesigning it. In this evaluation, we measured the execution speed and the dynamic characteristics of cache memory, register file, and branching hardware introduced for high-speed execution of Prolog programs.Execution speed of the PSI firmware interpreter was found to be comparable to that of the DEC-10 Prolog compiled code on the DEC-2060. It was also found that PSI was faster than DEC for executing programs containing much unification and backtracking that require runtime processing.With the cache memory, the hit ratio for application programs was found higher than 96%; this demonstrates that the Prolog execution has much memory access locality. The memory access frequency and the appearance ratio between Read and Write command were also investigated.Concerning the register file, use rate of each dedicated access mode was measured and effect of each mode was discussed. In the branching function we confirmed a high appearance rate of conditional branches and multi-way branches based on tag values.","PeriodicalId":117067,"journal":{"name":"Proceedings of the second international conference on Architectual support for programming languages and operating systems","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117178317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

A RISC architecture for symbolic computation 用于符号计算的RISC体系结构

Proceedings of the second international conference on Architectual support for programming languages and operating systems Pub Date : 1987-10-01 DOI: 10.1145/36206.36197

R. Kieburtz

引用次数: 15