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Proceedings of the second international conference on Architectual support for programming languages and operating systems最新文献

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Compiling Smalltalk-80 to a RISC 将Smalltalk-80编译为RISC
Proceedings of the second international conference on Architectual support for programming languages and operating systems Pub Date : 1987-10-01 DOI: 10.1145/36206.36192
W. Bush, A. D. Samples, D. Ungar, P. Hilfinger
{"title":"Compiling Smalltalk-80 to a RISC","authors":"W. Bush, A. D. Samples, D. Ungar, P. Hilfinger","doi":"10.1145/36206.36192","DOIUrl":"https://doi.org/10.1145/36206.36192","url":null,"abstract":"The Smalltalk On A RISC project at U. C. Berkeley proves that a high-level object-oriented language can attain high performance on a modified reduced instruction set architecture. The single most important optimization is the removal of a layer of interpretation, compiling the bytecoded virtual machine instructions into low-level, register-based, hardware instructions. This paper describes the compiler and how it was affected by SOAR architectural features. The compiler generates code of reasonable density and speed. Because of Smalltalk-80's semantics, relatively few optimizations are possible, but hardware and software mechanisms at runtime offset these limitations. Register allocation for an architecture with register windows comprises the major task of the compiler. Performance analysis suggests that SOAR is not simple enough; several hardware features could be efficiently replaced by instruction sequences constructed by the compiler.","PeriodicalId":117067,"journal":{"name":"Proceedings of the second international conference on Architectual support for programming languages and operating systems","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127365533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Pipelining and performance in the VAX 8800 processor VAX 8800处理器中的流水线和性能
Proceedings of the second international conference on Architectual support for programming languages and operating systems Pub Date : 1987-10-01 DOI: 10.1145/36206.36200
D. Clark
{"title":"Pipelining and performance in the VAX 8800 processor","authors":"D. Clark","doi":"10.1145/36206.36200","DOIUrl":"https://doi.org/10.1145/36206.36200","url":null,"abstract":"The VAX 8800 family (models 8800, 8700, 8550), currently the fastest computers in the VAX product line, achieve their speed through a combination of fast cycle time and deep pipelining. Rather than pipeline highly variable VAX instructions as such, the 8800 design pipelines uniform microinstructions whose addresses are generated by instruction unit hardware. This design approach helps achieve a fast cycle time, which is the prime determinan of performance. Some preliminary measurements of cycles per average instruction are reported.","PeriodicalId":117067,"journal":{"name":"Proceedings of the second international conference on Architectual support for programming languages and operating systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116570228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A VLIW architecture for a trace scheduling compiler 跟踪调度编译器的VLIW体系结构
Proceedings of the second international conference on Architectual support for programming languages and operating systems Pub Date : 1987-10-01 DOI: 10.1145/36206.36201
R. Colwell, R. Nix, J. O'Donnell, D. Papworth, P. Rodman
{"title":"A VLIW architecture for a trace scheduling compiler","authors":"R. Colwell, R. Nix, J. O'Donnell, D. Papworth, P. Rodman","doi":"10.1145/36206.36201","DOIUrl":"https://doi.org/10.1145/36206.36201","url":null,"abstract":"Very Long Instruction Word (VLIW) architectures were promised to deliver far more than the factor of two or three that current architectures achieve from overlapped execution. Using a new type of compiler which compacts ordinary sequential code into long instruction words, a VLIW machine was expected to provide from ten to thirty times the performance of a more conventional machine built of the same implementation technology.Multiflow Computer, Inc., has now built a VLIW called the TRACETM along with its companion Trace SchedulingTM compacting compiler. This new machine has fulfilled the performance promises that were made. Using many fast functional units in parallel, this machine extends some of the basic Reduced-Instruction-Set precepts: the architecture is load/store, the microarchitecture is exposed to the compiler, there is no microcode, and there is almost no hardware devoted to synchronization, arbitration, or interlocking of any kind (the compiler has sole responsibility for runtime resource usage).This paper discusses the design of this machine and presents some initial performance results.","PeriodicalId":117067,"journal":{"name":"Proceedings of the second international conference on Architectual support for programming languages and operating systems","volume":"197 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122682631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 505
An experimental coprocessor for implementing persistent objects on an IBM 4381 用于在IBM 4381上实现持久对象的实验性协处理器
Proceedings of the second international conference on Architectual support for programming languages and operating systems Pub Date : 1987-10-01 DOI: 10.1145/36206.36188
C. J. Georgiou, S. L. Palmer, P. L. Rosenfeld
{"title":"An experimental coprocessor for implementing persistent objects on an IBM 4381","authors":"C. J. Georgiou, S. L. Palmer, P. L. Rosenfeld","doi":"10.1145/36206.36188","DOIUrl":"https://doi.org/10.1145/36206.36188","url":null,"abstract":"In this paper we describe an experimental coprocessor for an IBM 4381 that is designed to facilitate the exploration of persistent objects.","PeriodicalId":117067,"journal":{"name":"Proceedings of the second international conference on Architectual support for programming languages and operating systems","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114228225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
The ZS-1 central processor ZS-1中央处理器
Proceedings of the second international conference on Architectual support for programming languages and operating systems Pub Date : 1987-10-01 DOI: 10.1145/36206.36203
James E. Smith, G. Dermer, B. D. Vanderwarn, S. Klinger, C. Rozewski, D. L. Fowler, K. R. Scidmore, J. Laudon
{"title":"The ZS-1 central processor","authors":"James E. Smith, G. Dermer, B. D. Vanderwarn, S. Klinger, C. Rozewski, D. L. Fowler, K. R. Scidmore, J. Laudon","doi":"10.1145/36206.36203","DOIUrl":"https://doi.org/10.1145/36206.36203","url":null,"abstract":"The Astronautics ZS-1 is a high speed, 64-bit computer system designed for scientific and engineering applications. The ZS-1 central processor uses a decoupled architecture, which splits instructions into two streams---one for fixed point/memory address computation and the other for floating point operations. The two instruction streams are then processed in parallel. Pipelining is also used extensively throughout the ZS-1.This paper describes the architecture and implementation of the ZS-1 central processor, beginning with some of the basic design objectives. Descriptions of the instruction set, pipeline structure, and virtual memory implementation demonstrate the methods used to satisfy the objectives. High performance is achieved through a combination of static (compile-time) instruction scheduling and dynamic (run-time) scheduling. Both types of scheduling are illustrated with examples.","PeriodicalId":117067,"journal":{"name":"Proceedings of the second international conference on Architectual support for programming languages and operating systems","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132432846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 88
Design tradeoffs to support the C programming language in the CRISP microprocessor 设计权衡支持C语言编程的CRISP微处理器
Proceedings of the second international conference on Architectual support for programming languages and operating systems Pub Date : 1987-10-01 DOI: 10.1145/36206.36198
D. Ditzel, H. McLellan
{"title":"Design tradeoffs to support the C programming language in the CRISP microprocessor","authors":"D. Ditzel, H. McLellan","doi":"10.1145/36206.36198","DOIUrl":"https://doi.org/10.1145/36206.36198","url":null,"abstract":"The CRISP Microprocessor contains a number of new architectural features to achieve high performance and support the C programming language, t The instruction set was designed to be independent of architectural tradeoffs used in any single implementation. This paper describes the particular tradeoffs used in the implementation of a 172,163 transistor 32-bit single chip microprocessor. 2 Many tradeoffs were used in the design of CRISP, this paper tries to focus on those particular to C.","PeriodicalId":117067,"journal":{"name":"Proceedings of the second international conference on Architectual support for programming languages and operating systems","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126627542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Proceedings of the second international conference on Architectual support for programming languages and operating systems 程序设计语言和操作系统的架构支持第二届国际会议论文集
Proceedings of the second international conference on Architectual support for programming languages and operating systems Pub Date : 1987-10-01 DOI: 10.1145/36206
R. Katz
{"title":"Proceedings of the second international conference on Architectual support for programming languages and operating systems","authors":"R. Katz","doi":"10.1145/36206","DOIUrl":"https://doi.org/10.1145/36206","url":null,"abstract":"","PeriodicalId":117067,"journal":{"name":"Proceedings of the second international conference on Architectual support for programming languages and operating systems","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126396211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
How many addressing modes are enough? 多少种寻址模式才足够?
Proceedings of the second international conference on Architectual support for programming languages and operating systems Pub Date : 1987-10-01 DOI: 10.1145/36206.36193
Fred C. Chow, Steven Correll, M. Himelstein, E. Killian, L. Weber
{"title":"How many addressing modes are enough?","authors":"Fred C. Chow, Steven Correll, M. Himelstein, E. Killian, L. Weber","doi":"10.1145/36206.36193","DOIUrl":"https://doi.org/10.1145/36206.36193","url":null,"abstract":"Programs naturally require a variety of memory-addressing modes. It isn't necessary to provide them in hardware, however, if a compiler can synthesize them from a few primitive modes. This not only simplifies the hardware, but also permits the compiler to use its understanding of the program to economize on the modes which it uses. We present some compilation techniques that allow the compiler to deal effectively with a single addressing mode in a target RISC processor. We also give measurements to show the benefits of such techniques, and to support our assertion that a single addressing mode is adequate for a general purpose processor, provided that mode incorporates both a pointer and an offset.","PeriodicalId":117067,"journal":{"name":"Proceedings of the second international conference on Architectual support for programming languages and operating systems","volume":"17 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116728652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
The dragon processor 龙处理器
Proceedings of the second international conference on Architectual support for programming languages and operating systems Pub Date : 1987-10-01 DOI: 10.1145/36206.36185
R. Atkinson, E. McCreight
{"title":"The dragon processor","authors":"R. Atkinson, E. McCreight","doi":"10.1145/36206.36185","DOIUrl":"https://doi.org/10.1145/36206.36185","url":null,"abstract":"The Xerox PARC Dragon is a VLSI research computer that uses several techniques to achieve dense code and fast procedure calls in a system that can support multiple processors on a central high bandwidth memory bus.","PeriodicalId":117067,"journal":{"name":"Proceedings of the second international conference on Architectual support for programming languages and operating systems","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125616616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Superoptimizer: a look at the smallest program 超级优化器:看看最小的程序
Proceedings of the second international conference on Architectual support for programming languages and operating systems Pub Date : 1987-10-01 DOI: 10.1145/36206.36194
H. Massalin
{"title":"Superoptimizer: a look at the smallest program","authors":"H. Massalin","doi":"10.1145/36206.36194","DOIUrl":"https://doi.org/10.1145/36206.36194","url":null,"abstract":"Given an instruction set, the superoptimizer finds the shortest program to compute a function. Startling programs have been generated, many of them engaging in convoluted bit-fiddling bearing little resemblance to the source programs which defined the functions. The key idea in the superoptimizer is a probabilistic test that makes exhaustive searches practical for programs of useful size. The search space is defined by the processor's instruction set, which may include the whole set, but it is typically restricted to a subset. By constraining the instructions and observing the effect on the output program, one can gain insight into the design of instruction sets. In addition, superoptimized programs may be used by peephole optimizers to improve the quality of generated code, or by assembly language programmers to improve manually written code.","PeriodicalId":117067,"journal":{"name":"Proceedings of the second international conference on Architectual support for programming languages and operating systems","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121597324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 343
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