2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)最新文献_第5页

RapidRoute: Fast Assembly of Communication Structures for FPGA Overlays RapidRoute: FPGA覆盖层通信结构的快速组装

2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2019-04-01 DOI: 10.1109/FCCM.2019.00018

Leo Liu, Jay Weng, Nachiket Kapre

引用次数: 6

Exploring the Random Network of Hodgkin and Huxley Neurons with Exponential Synaptic Conductances on OpenCL FPGA Platform 基于OpenCL FPGA平台的指数突触电导Hodgkin和Huxley神经元随机网络研究

2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2019-04-01 DOI: 10.1109/FCCM.2019.00057

Zheming Jin, H. Finkel

引用次数: 2

A Fine-Grained Parallel Snappy Decompressor for FPGAs Using a Relaxed Execution Model 使用放松执行模型的fpga细粒度并行快速减压器

2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2019-04-01 DOI: 10.1109/FCCM.2019.00076

Jian Fang, Jianyu Chen, Jinho Lee, Z. Al-Ars, H. P. Hofstee

引用次数: 7

Towards Prototyping and Acceleration of Java Programs onto Intel FPGAs Java程序在Intel fpga上的原型设计与加速

2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2019-04-01 DOI: 10.1109/FCCM.2019.00051

Michail Papadimitriou, J. Fumero, Athanasios Stratikopoulos, Christos Kotselidis

引用次数: 6

An FPGA-Based BWT Accelerator for Bzip2 Data Compression 基于fpga的Bzip2数据压缩BWT加速器

2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2019-04-01 DOI: 10.1109/FCCM.2019.00023

W. Qiao, Zhenman Fang, Mau-Chung Frank Chang, J. Cong

引用次数: 13

Rethinking Integer Divider Design for FPGA-Based Soft-Processors 基于fpga的软处理器整数除法器设计的再思考

2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2019-04-01 DOI: 10.1145/3502492

Eric Matthews, Alec Lu, Zhenman Fang, Lesley Shannon

{"title":"Rethinking Integer Divider Design for FPGA-Based Soft-Processors","authors":"Eric Matthews, Alec Lu, Zhenman Fang, Lesley Shannon","doi":"10.1145/3502492","DOIUrl":"https://doi.org/10.1145/3502492","url":null,"abstract":"Most existing soft-processors on FPGAs today support a fixed-latency instruction pipeline. Therefore, for integer division, a simple fixed-latency radix-2 integer divider is typically used, or algorithm-level changes are made to avoid integer divisions. However, for certain important application domains the simple radix-2 integer divider becomes the performance bottleneck, as every 32-bit division operation takes 32 cycles. In this paper, we explore integer divider designs for FPGA-based soft-processors, by leveraging the recent support of variable-latency execution units in their instruction pipeline. We implement a high-performance, data-dependent, variable-latency integer divider called Quick-Div, optimize its performance on FPGAs, and integrate it into a RISC-V soft-processor called Taiga that supports a variable-latency instruction pipeline. We perform a comprehensive analysis and comparison—in terms of cycles, clock frequency, and resource usage—for both the fixed-latency radix-2/4/8/16 dividers and our variable-latency Quick-Div divider with various optimizations. Experimental results on a Xilinx Virtex UltraScale+ VCU118 FPGA board show that our Quick-Div divider can provide over 5x better performance and over 4x better performance/LUT compared to a radix-2 divider for certain applications like random number generation. Finally, through a case study of integer square root, we demonstrate that our Quick-Div divider provides opportunities for reconsidering simpler and faster algorithmic choices.","PeriodicalId":116955,"journal":{"name":"2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122992551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

An OpenCL-Based Acceleration for Canny Algorithm Using a Heterogeneous CPU-FPGA Platform 基于opencl的Canny算法异构CPU-FPGA加速

2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2019-04-01 DOI: 10.1109/FCCM.2019.00063

Samah Rahamneh, L. Sawalha

引用次数: 2

Automated Design Space Exploration and Roofline Analysis for FPGA-Based HLS Applications 基于fpga的HLS应用的自动设计空间探索和车顶线分析

2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2019-04-01 DOI: 10.1109/FCCM.2019.00055

Marco Siracusa, Marco Rabozzi, Emanuele Del Sozzo, M. Santambrogio, Lorenzo Di Tucci

引用次数: 5

LUTNet: Rethinking Inference in FPGA Soft Logic FPGA软逻辑推理的再思考

2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2019-04-01 DOI: 10.1109/FCCM.2019.00014

Erwei Wang, James J. Davis, P. Cheung, G. Constantinides

{"title":"LUTNet: Rethinking Inference in FPGA Soft Logic","authors":"Erwei Wang, James J. Davis, P. Cheung, G. Constantinides","doi":"10.1109/FCCM.2019.00014","DOIUrl":"https://doi.org/10.1109/FCCM.2019.00014","url":null,"abstract":"Research has shown that deep neural networks contain significant redundancy, and that high classification accuracies can be achieved even when weights and activations are quantised down to binary values. Network binarisation on FPGAs greatly increases area efficiency by replacing resource-hungry multipliers with lightweight XNOR gates. However, an FPGA's fundamental building block, the K-LUT, is capable of implementing far more than an XNOR: it can perform any K-input Boolean operation. Inspired by this observation, we propose LUTNet, an end-to-end hardware-software framework for the construction of area-efficient FPGA-based neural network accelerators using the native LUTs as inference operators. We demonstrate that the exploitation of LUT flexibility allows for far heavier pruning than possible in prior works, resulting in significant area savings while achieving comparable accuracy. Against the state-of-the-art binarised neural network implementation, we achieve twice the area efficiency for several standard network models when inferencing popular datasets. We also demonstrate that even greater energy efficiency improvements are obtainable.","PeriodicalId":116955,"journal":{"name":"2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124242525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 49

Wire-Speed Multirate Accelerator for Aggregation Operations on Sorted Data 用于排序数据聚合操作的线速多速率加速器

2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2019-04-01 DOI: 10.1109/FCCM.2019.00065

S. Jun, A. Arvind

引用次数: 0