2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)最新文献_第6页

GhostSZ: A Transparent FPGA-Accelerated Lossy Compression Framework GhostSZ:一个透明的fpga加速有损压缩框架

2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2019-04-01 DOI: 10.1109/FCCM.2019.00042

Qingqing Xiong, Rushi Patel, Chen Yang, Tong Geng, A. Skjellum, M. Herbordt

{"title":"GhostSZ: A Transparent FPGA-Accelerated Lossy Compression Framework","authors":"Qingqing Xiong, Rushi Patel, Chen Yang, Tong Geng, A. Skjellum, M. Herbordt","doi":"10.1109/FCCM.2019.00042","DOIUrl":"https://doi.org/10.1109/FCCM.2019.00042","url":null,"abstract":"High-performance computing (HPC) applications often generate enormous amounts of data that must be transferred for check-pointing, in situ processing, or post-execution analysis. To reduce the related network traffic and storage consumption, lossy compression schemes that target scientific data are often used. SZ compression emerged three years ago and has gained much attention because of its high compression ratio. However, performing SZ compression can take half a day per Terabyte of data; this could be a drawback to adoption. We propose GhostSZ an FPGA framework for accelerating tasks in SZ at line rate, and so transparently. The critical problem to be overcome is the tight data dependence central to SZ. GhostSZ solves this with a data transfer path having novel staged hardware. We test our implementation with both synthetic and real HPC application data and show 9.5×-80× core versus pipeline speedup over the optimized production version running on a state-of-the-art CPU and 8.2× per chip. Much of the variance in performance is due to the FPGA already running at line rate and so benefiting less from optimizations applicable to the CPU only on the most favorable data sets. The significance of this work is the possibility of a major reduction in required networking and storage in HPC installations. For example, using GhostSZ, fewer than 10 FPGAs would be sufficient to handle the entire I/O bandwidth of the top entry on the latest IO-500 list.","PeriodicalId":116955,"journal":{"name":"2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)","volume":"281 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116073975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Flexi-AES: A Highly-Parameterizable Cipher for a Wide Range of Design Constraints 灵活aes:一种适用于广泛设计约束的高度可参数化密码

2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2019-04-01 DOI: 10.1109/FCCM.2019.00079

Sergiu Mosanu, Xinfei Guo, Mohamed El-Hadedy, L. Anghel, M. Stan

引用次数: 6

Large-Scale and High-Throughput QR Decomposition on an FPGA 基于FPGA的大规模高通量QR分解

2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2019-04-01 DOI: 10.1109/FCCM.2019.00078

Dajung Lee, A. Hagiescu, Dan Pritsker

引用次数: 3

Efficient Hardware Acceleration for Design Diversity Calculation to Mitigate Common Mode Failures 设计分集计算的有效硬件加速以减少共模故障

2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2019-04-01 DOI: 10.1109/FCCM.2019.00043

M. R. Babu, Farah Naz Taher, Anjana Balachandran, Benjamin Carrión Schäfer

引用次数: 0

Scalable P4 Deparser for Speeds Over 100 Gbps 可扩展的P4分离器，速度超过100 Gbps

2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2019-04-01 DOI: 10.1109/FCCM.2019.00064

Jakub Cabal, Pavel Benácek, Jana Foltova, J. Holub

引用次数: 3

Templatised Soft Floating-Point for High-Level Synthesis 用于高级综合的模板化软浮点

2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2019-04-01 DOI: 10.1109/FCCM.2019.00038

David B. Thomas

{"title":"Templatised Soft Floating-Point for High-Level Synthesis","authors":"David B. Thomas","doi":"10.1109/FCCM.2019.00038","DOIUrl":"https://doi.org/10.1109/FCCM.2019.00038","url":null,"abstract":"High-level Synthesis (HLS) tools have greatly increased the productivity of FPGA application development, making it possible to easily create highly-parallel application-accelerators. However, while FPGAs are known for the ability to customise the number representation of data-paths, most HLS work only uses custom-precision for fixed-point representations, and for floating-point relies on the 64-, 32-, and 16-bitformats provided by vendors. This paper presents a solution for parametrised floating-point in HLS via C++ templates, allowing for compile-time selection of exponent and fraction widths, including the use of mixed precisions for input arguments and result types. By using arbitrary width integers and compile-time logic the resulting operators describe the same data-path as an external floating-point IP generator, while still allowing the HLS tool to perform detailed optimisation and scheduling of the internal components. We show that the resulting custom-width HLS cores provide similar area and performance to platform-native vendor IP blocks, while adding full support for heterogeneous precision floating-point data-paths to HLS tools.","PeriodicalId":116955,"journal":{"name":"2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131276615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Automated Acceleration of Dataflow-Oriented C Applications on FPGA-Based Systems 基于fpga的系统中面向数据流的C语言应用的自动加速

2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2019-04-01 DOI: 10.1109/FCCM.2019.00054

Francesco Peverelli, Marco Rabozzi, Salvatore Cardamone, Emanuele Del Sozzo, A. Thom, M. Santambrogio, Lorenzo Di Tucci

引用次数: 1

Model-Extraction Attack Against FPGA-DNN Accelerator Utilizing Correlation Electromagnetic Analysis 基于相关电磁分析的FPGA-DNN加速器模型提取攻击

2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2019-04-01 DOI: 10.1109/FCCM.2019.00059

Kota Yoshida, Takaya Kubota, M. Shiozaki, T. Fujino

引用次数: 18

Analyzing the Energy-Efficiency of Vision Kernels on Embedded CPU, GPU and FPGA Platforms 嵌入式CPU、GPU和FPGA平台上视觉内核的能效分析

2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2019-04-01 DOI: 10.1109/FCCM.2019.00077

Murad Qasaimeh, Joseph Zambreno, Phillip H. Jones, K. Denolf, Jack Lo, K. Vissers

引用次数: 14

Memory Mapping for Multi-die FPGAs 多芯片fpga的内存映射

2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) Pub Date : 2019-04-01 DOI: 10.1109/FCCM.2019.00021

Nils Voss, Pablo Quintana, O. Mencer, W. Luk, G. Gaydadjiev

引用次数: 12