2020 IEEE 33rd International System-on-Chip Conference (SOCC)最新文献_第6页

AutoML for Multilayer Perceptron and FPGA Co-design 多层感知器的自动化与FPGA协同设计

2020 IEEE 33rd International System-on-Chip Conference (SOCC) Pub Date : 2020-09-08 DOI: 10.1109/socc49529.2020.9524785

Philip Colangelo, Oren Segal, Alexander Speicher, M. Margala

{"title":"AutoML for Multilayer Perceptron and FPGA Co-design","authors":"Philip Colangelo, Oren Segal, Alexander Speicher, M. Margala","doi":"10.1109/socc49529.2020.9524785","DOIUrl":"https://doi.org/10.1109/socc49529.2020.9524785","url":null,"abstract":"Optimizing neural network architectures (NNA) is a difficult process in part because of the vast number of hyperparameter combinations that exist. The difficulty in designing performant neural networks has brought a recent surge in interest in the automatic design and optimization of neural networks. The focus of the existing body of research has been on optimizing NNA for accuracy [1] [2] with publications starting to address hardware optimizations [3]. Our focus is to close this gap by using evolutionary algorithms to search an entire design space, including NNA and reconfigurable hardware. Large data-centric companies such as Facebook[4] [5] and Google [6] have published data showing that MLP workloads are the majority of their application base. Facebook cites the use of MLP for tasks such as determining which ads to display, which stories matter to see in a news feed, and which results to present from a search. Park et al. stress the importance of these networks and the current limitations on standard hardware and the call for what this research aims to solve, i.e., software and hardware co-design in [7]. Our research aims to take advantage of the reconfigurable architecture of an FPGA device that is capable of molding to a specific workload and neural network structure. Leveraging evolutionary algorithms to search the entire design space of both MLP and target hardware simultaneously, we find unique solutions that achieve both top accuracy and optimal hardware performance.","PeriodicalId":114740,"journal":{"name":"2020 IEEE 33rd International System-on-Chip Conference (SOCC)","volume":"06 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129984640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

ASIC Power Estimation Across Revisions using Machine Learning 使用机器学习跨版本的ASIC功率估计

2020 IEEE 33rd International System-on-Chip Conference (SOCC) Pub Date : 2020-09-08 DOI: 10.1109/socc49529.2020.9524795

Ali Tariq, Howard Yang

引用次数: 0

Cycle-to-cycle Variation Enabled Energy Efficient Privacy Preserving Technology in ANN 基于周期间变化的人工神经网络节能隐私保护技术

2020 IEEE 33rd International System-on-Chip Conference (SOCC) Pub Date : 2020-09-08 DOI: 10.1109/socc49529.2020.9524794

Jingyan Fu, Zhiheng Liao, Jinhui Wang

引用次数: 3

Analog Content Addressable Memory using Ferroelectric: A Case Study of Search-in-Memory 使用铁电的模拟内容可寻址存储器:存储器中搜索的案例研究

2020 IEEE 33rd International System-on-Chip Conference (SOCC) Pub Date : 2020-09-08 DOI: 10.1109/socc49529.2020.9524766

Chuangtao Chen, Qingrong Huang, Chao Li, Li Zhang, Cheng Zhuo, Xunzhao Yin

{"title":"Analog Content Addressable Memory using Ferroelectric: A Case Study of Search-in-Memory","authors":"Chuangtao Chen, Qingrong Huang, Chao Li, Li Zhang, Cheng Zhuo, Xunzhao Yin","doi":"10.1109/socc49529.2020.9524766","DOIUrl":"https://doi.org/10.1109/socc49529.2020.9524766","url":null,"abstract":"Non-volatile (NV) devices are actively considered for compact and high performance memory architectures, especially in-memory computing (IMC) designs where processing and memory elements are co-located to address the memory wall issues for data-intensive applications. Content addressable memories (CAMs) are a form of IMC that compares the input query data against the stored data in parallel, and outputs the comparison result in terms of match or mismatch. Numerous CAMs have been proposed based on NV devices and demonstrate superior area, energy and performance metrics over the CMOS based conventional ones. Unlike the prior works that exploit the NV devices in the digital domain, in this paper, we proposed an analog CAM design, which utilizes the analog characteristics of Ferroelectrics field effect transistor (FeFET) to achieve a denser storage and search operations in analog domain. We illustrate our proposed analog CAM through a device-circuit co-design approach, and validate the 3-bit storage and search capability of the proposed design. The scalability of the proposed design is also examined. Evaluation results suggests that our analog CAM can achieve 22.4 × higher memory density, and 8.6 × higher energy efficiency compared with the conventional CMOS based design.","PeriodicalId":114740,"journal":{"name":"2020 IEEE 33rd International System-on-Chip Conference (SOCC)","volume":"213 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131319777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Downlink-Centric User Scheduling for Full-Duplex MU-MIMO Systems 为全双工MU-MIMO系统Downlink-Centric用户调度

2020 IEEE 33rd International System-on-Chip Conference (SOCC) Pub Date : 2020-09-08 DOI: 10.1109/socc49529.2020.9524789

Jianhua Zhang, M. Zou, Lai Wei, Meng Ma, B. Jiao

引用次数: 0

Cube Attack on a Trojan-Compromised Hardware Implementation of Ascon 基于立方体攻击的Ascon木马硬件实现

2020 IEEE 33rd International System-on-Chip Conference (SOCC) Pub Date : 2020-09-08 DOI: 10.1109/socc49529.2020.9524771

Basel Halak, Jorge Duarte-Sanchez

引用次数: 0

The IANET Hardware Accelerator for Audio and Visual Data Classification 用于视听数据分类的IANET硬件加速器

2020 IEEE 33rd International System-on-Chip Conference (SOCC) Pub Date : 2020-09-08 DOI: 10.1109/socc49529.2020.9524782

Rohini J. Gillela, A. Ganguly, D. Patru, Mark A. Indovina

{"title":"The IANET Hardware Accelerator for Audio and Visual Data Classification","authors":"Rohini J. Gillela, A. Ganguly, D. Patru, Mark A. Indovina","doi":"10.1109/socc49529.2020.9524782","DOIUrl":"https://doi.org/10.1109/socc49529.2020.9524782","url":null,"abstract":"There are several instances during driving where audible data is of importance, though often ignored. Today's deaf or acoustically impaired drivers face challenges during driving in various countries. They are vulnerable as they can't hear the siren or vehicle horn and depend on other drivers around them to act. Processing audio and providing feedback would be equally valuable to any driver or autonomous vehicle. This paper addresses the gap in existing technology by integrating audio or acoustic and image or visual processing units with the help of efficient hardware design and architecture of the Convolutional Neural Networks (CNNs). These processing units are integrated into a single module, IANET, that makes use of two CNN accelerators, one for audio and the other for image processing units. The hardware is implemented in various fixed-point representations to observe the accuracy and stability of network classifiers at each representation. The hardware accelerators for image and audio classification achieve a throughput of 30 frames per second (fps) at 180 MHz and 1 fps at 20 MHz, respectively. This paper presents the power and area-efficient hardware implementation of IANET.","PeriodicalId":114740,"journal":{"name":"2020 IEEE 33rd International System-on-Chip Conference (SOCC)","volume":"205 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122779837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Dynamic Expansion Order Algorithm for the SAT-based Minimization 一种基于sat的动态扩展阶算法

2020 IEEE 33rd International System-on-Chip Conference (SOCC) Pub Date : 2020-09-08 DOI: 10.1109/socc49529.2020.9524758

Chia-Chun Lin, Kit Seng Tam, Chana-Cheng Ko, Hsin-Ping Yen, Shenz-Hsiu Wei, Yung-Chih Chen, Chun-Yao Wang

引用次数: 0

Proceedings 33rd IEEE International System on Chip Conference (SOCC) [Front matter] 第33届IEEE国际芯片系统会议论文集[前沿事项]

2020 IEEE 33rd International System-on-Chip Conference (SOCC) Pub Date : 2020-09-08 DOI: 10.1109/socc49529.2020.9524723

引用次数: 0

Hierarchical Active Voltage Regulation for Heterogeneous TSV 3D-ICs 异质TSV三维集成电路的分层有源电压调节

2020 IEEE 33rd International System-on-Chip Conference (SOCC) Pub Date : 2020-09-08 DOI: 10.1109/socc49529.2020.9524797

Po-Tsang Huang, Tzung-Han Tsai, Po-Jen Yang, W. Hwang, Hung-Ming Chen

{"title":"Hierarchical Active Voltage Regulation for Heterogeneous TSV 3D-ICs","authors":"Po-Tsang Huang, Tzung-Han Tsai, Po-Jen Yang, W. Hwang, Hung-Ming Chen","doi":"10.1109/socc49529.2020.9524797","DOIUrl":"https://doi.org/10.1109/socc49529.2020.9524797","url":null,"abstract":"Among different system-in-package (SiP) technologies, through-silicon-via (TSV) 3D-IC is the key to the success of future heterogeneous SiP integration due to the high interconnect density. In heterogeneous TSV 3D integration, however, the increasing current density through both package and TSVs would lead to a large simultaneous switching noise (SSN) potentially. In this paper, a 3D power network with hierarchical active voltage regulation is proposed to reduce dynamic noises for heterogeneous TSV 3D-ICs. For the hierarchical active voltage regulation, the global power network and the local power networks are decoupled by fully-integrated voltage regulators (FIVRs). Furthermore, active switched decoupling capacitors (DECAPs) and distributed FIVRs are adopted as the global regulator and local regulators, respectively. Additionally, a substrate noise suppression technique is also presented to enhance the power integrity by reducing both substrate and TSV coupling noises. These techniques achieve not only for reducing the required DECAPs but providing flexible power sources. The modeling and simulation results of a heterogeneous TSV 3D integration demonstrate that the noise reduction on power supply pairs (VDD & GND) are suppressed by up to 71.10% with only 1.11% power overhead.","PeriodicalId":114740,"journal":{"name":"2020 IEEE 33rd International System-on-Chip Conference (SOCC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-09-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125927021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0