Hierarchical Active Voltage Regulation for Heterogeneous TSV 3D-ICs

Abstract

Among different system-in-package (SiP) technologies, through-silicon-via (TSV) 3D-IC is the key to the success of future heterogeneous SiP integration due to the high interconnect density. In heterogeneous TSV 3D integration, however, the increasing current density through both package and TSVs would lead to a large simultaneous switching noise (SSN) potentially. In this paper, a 3D power network with hierarchical active voltage regulation is proposed to reduce dynamic noises for heterogeneous TSV 3D-ICs. For the hierarchical active voltage regulation, the global power network and the local power networks are decoupled by fully-integrated voltage regulators (FIVRs). Furthermore, active switched decoupling capacitors (DECAPs) and distributed FIVRs are adopted as the global regulator and local regulators, respectively. Additionally, a substrate noise suppression technique is also presented to enhance the power integrity by reducing both substrate and TSV coupling noises. These techniques achieve not only for reducing the required DECAPs but providing flexible power sources. The modeling and simulation results of a heterogeneous TSV 3D integration demonstrate that the noise reduction on power supply pairs (VDD & GND) are suppressed by up to 71.10% with only 1.11% power overhead.