ASIC Power Estimation Across Revisions using Machine Learning

Abstract

ASIC chip revisions often include major changes, such as new features, timing updates, and bug fixes. It is important to be able to accurately estimate dynamic and leakage power for these changes, during the architectural planning stage. Using physical design data from prior revisions, we can train machine learning models that can predict standard cell power within 15% to 40% of the post-route implementation for the new ASIC. We also look at multiple different machine learning frameworks to find the optimal solution for this problem.