{"title":"On N-Shaped I-V Characteristic Devices with Memristive Behavior","authors":"T. Wey","doi":"10.1109/NEWCAS.2018.8585604","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585604","url":null,"abstract":"The small-signal model of an n-shaped I-V characteristic device with a resistance memory (memristor) is considered in this work. The implications of this memristance property on a typical application of these devices in negative differential resistance oscillators is considered. It is shown thru theory and simulation that the n-shaped I-V device with memristance demonstrates distinct differences from the device without memristance.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134105333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An 11.2nW, 0.45V PVT-tolerant Pulse-width Modulated Temperature Sensor in 65 nm CMOS","authors":"A. Azam, Zhidong Bai, J. Walling","doi":"10.1109/NEWCAS.2018.8585691","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585691","url":null,"abstract":"This paper presents a low power temperature sensor in 65 nm CMOS. The architecture is digital friendly because it creates a pulse-width modulated (PWM) output instead of a DC voltage; hence, it can be directly interfaced with a digital counter instead of a power-hungry analog-to-digital converter. The proposed design does not use a reference current, which is the prime energy consumer in most temperature sensors, due to required feedback amplifiers. Additionally, reference current devices require large voltage headroom while their resistors occupy large die area. The proposed design expresses the output as a ratio, relative to a reference pulse. Therefore, it is less susceptible to process-voltage-temperature (PVT) variation. The proposed design achieves a temperature accuracy of +0.23°C to-0.22°C within the temperature range-20-80°C, while consuming only 11.2nW at 27°C, while operating from a supply voltage as low as 450 mV.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114201800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Reliability Analysis of CMOS Rambus Oscillator under Device Mismatch Effects","authors":"Ibtissem Seghaier, S. Tahar","doi":"10.1109/NEWCAS.2018.8585623","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585623","url":null,"abstract":"This paper introduces an approach that uses transient sensitivity analysis and state space verification to assess the reliability of Rambus oscillators due to device mismatch. The transient sensitivity analysis aims to truncate the high dimensional parameter variations space into a reduced subspace. Thereafter, a phase-space pattern matching verification approach is performed on this reduced subspace to estimate the yield rate using new measures called Recurrence Rate and Recurrence Periodicity Entropy. The proposed approach is illustrated on a four stage CMOS Rambus oscillator. The obtained results demonstrate a far faster yield assessment with a superior accuracy compared to Monte Carlo technique.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"458 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117014388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Parihar, A. Anvesha, M. Jerry, S. Datta, A. Raychowdhury
{"title":"Dynamics of Coupled Systems and their Computing Properties Invited Paper : Invited Paper","authors":"A. Parihar, A. Anvesha, M. Jerry, S. Datta, A. Raychowdhury","doi":"10.1109/NEWCAS.2018.8585589","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585589","url":null,"abstract":"Collective dynamical systems offer unique opportunities for computing by harnessing the complex interactions of simple elements such as oscillators or spike generators. This is possible when such dynamics can be programmed, controlled, and observed. In this talk, we will present some of our work where we are exploring the timeevolution of both deterministic and stochastic dynamical systems in both CMOS and post-CMOS computing substrates. Such systems find applications in solving inverse problems, distributed optimizations (convex and combinatorial) and machine learning. In this paper we will discuss our recent work that connects dynamics and algebraic graph theory. We will talk about implementation of such dynamics in mixed-signal CMOS, including a recent demonstration of reinforcement learning for energy-constrained edge devices. We will conclude with a brief discussion of the opportunities, potentials and challenges in realizing such computational systems.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126972820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"FPGA Based True Random Number Generators Using Non-Linear Feedback Ring Oscillators","authors":"S. Tao, Yang Yu, E. Dubrova","doi":"10.1109/NEWCAS.2018.8585569","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585569","url":null,"abstract":"True random number generators (TRNGs) are important hardware primitives required for many applications including cryptography, communication, and statistical simulation. This paper presents a non-linear feedback ring oscillator (NL-FRO) based entropy source for implementing high performance TRNGs on FPGAs. The proposed NLFRO structures harvest randomness from noise and unpredictable variation in delay cells and bi-stable elements which are further amplified by non-linear feedback loops. The outputs of NLFROs show chaotic behavior, making them suitable for implementing high entropy, high speed and attack resistance TRNGs. Three NLFRO-TRNGs are implemented and tested on an Altera 60nm FPGA device. Raw entropy and statistical properties of the NLFRO-TRNGs are examined by the NIST 800-22 entropy estimation and NIST 800-90B statistical test suits. Compared to the prior art, experimental NLFRO-TRNGs show higher entropy and lower resource usage while consuming sub-milliwatt at 200 Mbps.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125850554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"RF Energy Harvesting For Self Powered Sensor Platform","authors":"N. Radhika, P. Tandon, T. Prabhakar, K. Vinoy","doi":"10.1109/NEWCAS.2018.8585659","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585659","url":null,"abstract":"This work demonstrates a RF powered sensor platform where energy can be available either in ambient FM band or emitted from a dedicated RF source. We realized the requirement with a dedicated chip built for RF power harvesting and conditioning. A switched capacitor based ultra low power DC-DC boost converter is designed in 130nm CMOS technology as energy harvesting circuitry for ambient RF. The on-chip RF-DC resulted in a maximum efficiency of 44% with 9.75k resistive load. At input sensitivities of -16dBm over 8 dominant frequencies, the sensor platform with strain gauge as sensor advertised a BLE packet every 20 minutes. For dedicated emitted radiations, the designed hybrid system is powered using sub-1 GHz frequencies. The resulting system has an end-to-end system efficiency of 9.1% and packet transmission interval of 90 seconds.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127546158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Linjun He, Chenchang Zhan, Yang Nan, Ning Zhang, Lidan Wang, Guofeng Li
{"title":"A 0.5V 46.2ppm°C CMOS Voltage Reference Based on Compensated ΔVTH with Wide Temperature Range and High PSRR","authors":"Linjun He, Chenchang Zhan, Yang Nan, Ning Zhang, Lidan Wang, Guofeng Li","doi":"10.1109/NEWCAS.2018.8585544","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585544","url":null,"abstract":"This paper presents a CMOS voltage reference (CVR) with low power, high power supply ripple rejection (PSRR), and small area operating in a wide temperature range. The proposed circuit contains only MOSFETs biased in subthreshold region and operates based on compensated Δ ${mathbf{V}}_{mathbf{TH}}$ of two different-type transistors. Implemented in a standard 0.18$mu mathbf{m}$ CMOS process, the measured reference voltage of the proposed CVR is 344 mV with standard deviation of only 2.89 mV and achieves an average TC of 46.2ppm°C over a wide temperature range from - 40 °C to 125°C without individual chip-by-chip trimming. The measured PSRR is -70 dB, -51 dB and -52 dB at 10 Hz, 100 kHz and 10 MHz, respectively. The measured line sensitivity (LS) is 0.25%/V while consuming 15.65nW at 0.5V supply. The active area is 0.019$mm^{mathbf{2}}$.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129779257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Implementation of a Chaotic True Random Number Generator Based on Fuzzy Modeling","authors":"T. Nguyen, Georges Kaddoum, F. Gagnon","doi":"10.1109/NEWCAS.2018.8585501","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585501","url":null,"abstract":"The present work demonstrates a new approach to design a chaos-based random number generator, for high-security communications and cryptographic applications. In our approach, a single-scroll chaotic system is modeled by a fuzzy logic circuit, with the support of physical entropy sources. Because of a strong dependence on the initial conditions of the chaotic system, physical entropy sources are chosen to enrich the randomness of the overall signal outcome. The modeling of the chaotic map by fuzzy logic circuits enhance the system immunity to noise and assure a certain degree of parameter deviation robustness. The frequency, operating up to 10 MHz, provides high throughput random sequences, which pass the test of full NIST random number test suite. The system is implemented in an analog circuit using a standard CMOS 65nm technology to verify the advantages of the proposed system.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126464398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Dang-Kièn Germain Pham, G. Gagnon, F. Gagnon, Georges Kaddoum, C. Jabbour, P. Desgreys
{"title":"FFT-Based Limited Subband Digital Predistortion Technique for Ultra Wideband 5G Systems","authors":"Dang-Kièn Germain Pham, G. Gagnon, F. Gagnon, Georges Kaddoum, C. Jabbour, P. Desgreys","doi":"10.1109/NEWCAS.2018.8585582","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585582","url":null,"abstract":"Parallel subband digital predistortion (DPD) has emerged as a promising approach for linearizing power amplifiers (PA) in wireless communication systems. This solution has the advantage of relaxing the bandwidth constraints on the feedback path analog to digital converter (ADC) which digitizes the PA distorted output which may spread over several hundreds MHz in the latest generations of mobile communications. However, the subband approach still has some limitations such as signal reconstruction and subband aliasing which limits its implementation on a wide scale. In this paper, an FFT-Based DPD technique that enables to compute the predistorter without interpolating signals is presented. Thanks to the frequency domain approach, the subband signals can be combined easily to compute the fullband predistorter directly. Moreover, the proposed technique offers the possibility of selecting specific frequency bins for the computation. In particular, the subband edges can be ignored which will result in relaxed bandwidth constraints and selectivity for the subband ADCs. Simulations show that the proposed FFT based subband DPD performs as good as the conventional time domain least-square approach even while excluding up to 13% of the FFT bins at the band edges.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127683901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Beamforming for Powerline Interference in Large Sensor Arrays","authors":"Manouane Caza-Szoka, D. Massicotte, F. Nougarou","doi":"10.1109/NEWCAS.2018.8585510","DOIUrl":"https://doi.org/10.1109/NEWCAS.2018.8585510","url":null,"abstract":"This paper shows how to use beamforming to remove the power-line interference (PLI) in large surface electromyography (sEMG) sensor array or high-density sEMG. The method exploits the highly correlated nature of the different sources of interference, being part of the same electrical grid, and their narrow frequency bands. The idea is to use a very narrow pass-band filter around 50 or 60 Hz to get signals with high PLI content before applying a spatial filtering by principal component analysis (PCA). This way, beamforming are done on the frequency bands where PLI are presents. Also, it ensures that even if the PLI has a smaller overall power than the desired signal, it will be easily found as the most powerful component of the decomposition. The PLI can then be removed from the signal. With trivial modification, harmonics of the PLI can also be removed. The approach was used in the context of muscle behavior analyses of low back pain patients using a sEMG array of 64 sensors. The performances of the filter are studied by experimental and semi-empirical methods. Compared to the usual notch filter, an improvement of up 10 dB is found.","PeriodicalId":112526,"journal":{"name":"2018 16th IEEE International New Circuits and Systems Conference (NEWCAS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132975505","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}