发布求助
文献互助 智能选刊 最新文献

2012 Brazilian Symposium on Computing System Engineering最新文献

筛选
英文 中文
Natural Landmark Tracking Method to Support UAV Navigation over Rain Forest Areas 支持无人机在热带雨林地区导航的自然地标跟踪方法
2012 Brazilian Symposium on Computing System Engineering Pub Date : 2012-11-05 DOI: 10.1109/SBESC.2012.28
F. Pinage, José Reginaldo H. Cavalho, J. P. Queiroz-Neto
{"title":"Natural Landmark Tracking Method to Support UAV Navigation over Rain Forest Areas","authors":"F. Pinage, José Reginaldo H. Cavalho, J. P. Queiroz-Neto","doi":"10.1109/SBESC.2012.28","DOIUrl":"https://doi.org/10.1109/SBESC.2012.28","url":null,"abstract":"Field application of unmanned aerials systems (UASs) have increased in the last decade, with special focus on missions in which there is any kind of risk for the crew. However, in some situations the lack of onboard pilots makes the mission execution a very difficult task. As an example one has long endurance missions over rain forest, and glacial areas, due to the uniform patterns. In this scenario an embedded vision system plays a critical role on both remotely operated and autonomous navigation modes. This paper presents an approach towards a vision system model able to track landmarks in forest areas, as a navigation support for UASs. This system consists of two main steps: (1) multiresolution decomposition and nonrelevant features suppression techniques based on wavelet; and (2) automatic control points identification and matching for sensed video frame and reference image. Preliminary results demonstrated that this model can correctly track a sequence of natural landmarks while suppressing nonrelevant features.","PeriodicalId":112286,"journal":{"name":"2012 Brazilian Symposium on Computing System Engineering","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134041090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A LLVM Based Development Environment for Embedded Systems Software Targeting the RISCO Processor 基于LLVM的RISCO处理器嵌入式系统软件开发环境
2012 Brazilian Symposium on Computing System Engineering Pub Date : 2012-11-05 DOI: 10.1109/SBESC.2012.23
Giuliano Vilela, E. Corrêa, M. Kreutz
{"title":"A LLVM Based Development Environment for Embedded Systems Software Targeting the RISCO Processor","authors":"Giuliano Vilela, E. Corrêa, M. Kreutz","doi":"10.1109/SBESC.2012.23","DOIUrl":"https://doi.org/10.1109/SBESC.2012.23","url":null,"abstract":"In this paper we describe the design and implementation of a compilation and code analysis toolchain for embedded systems software targeting the RISCO processor, using the LLVM project. Small systems embedded in a larger device are by far the most common kind of computational system in use today, deployed in various types of equipments. Because of their nature, an embedded system presents interesting size, efficiency and energy consumption restrictions, among others, that impose unique challenges on a project. In that scenario, the RISCO processor, a RISC architecture similar to MIPS, was created as a simple, efficient, processor that could prove to be a practical alternative to the available commercial options in its price range. The toolchain we developed permit the development, simulation and analysis of software in C and C++ for the RISCO platform, with open source tools. Besides compiling and executing high level code, the environment supports emitting control flow graphs for each module, enabling further analysis. As a case study on using CFGs and generated machine code information we developed a worst case execution time analysis tool for RISCO code. We discuss the scope of the tools, the design decisions involved in the development of the compilation and analysis system, and the results obtained through testing.","PeriodicalId":112286,"journal":{"name":"2012 Brazilian Symposium on Computing System Engineering","volume":"249 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132657556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Energy Profile Evaluation of a Cyber-Physical System 信息物理系统的能量剖面评估
2012 Brazilian Symposium on Computing System Engineering Pub Date : 2012-11-05 DOI: 10.1109/SBESC.2012.19
Elisabete Nakoneczny Moraes, L. Becker
{"title":"Energy Profile Evaluation of a Cyber-Physical System","authors":"Elisabete Nakoneczny Moraes, L. Becker","doi":"10.1109/SBESC.2012.19","DOIUrl":"https://doi.org/10.1109/SBESC.2012.19","url":null,"abstract":"In Cyber-Physical Systems (CPS) the operation of electromechanical devices is tightly integrated with the embedded computer system. The diversity of components imply in different profiles of energy consumption. Thereby, it becomes useful to use techniques that can manage the energy consumption. In a previous work, this aspect was modeled using a technique that allows estimating the energy consumption of a battery-powered CPS. In this paper we present a practical implementation of such work, where the peripherals of a mobile robotic system are characterized to compose the energy profile of the system. Conducted experiments measured the electrical currents during a planned navigation of the robot. The results confirm the assumptions assumed by the modeling technique, which proposes a relationship between the embedded computer system and the electromechanical devices, i.e., there is a direct relation between the device's activation and the nature of the software task under execution.","PeriodicalId":112286,"journal":{"name":"2012 Brazilian Symposium on Computing System Engineering","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131792122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
JingleOS: An Operating System to Embedded Devices with Language-Based Protection 基于语言保护的嵌入式设备操作系统
2012 Brazilian Symposium on Computing System Engineering Pub Date : 2012-11-05 DOI: 10.1109/SBESC.2012.15
L. Tenorio, S. Meira
{"title":"JingleOS: An Operating System to Embedded Devices with Language-Based Protection","authors":"L. Tenorio, S. Meira","doi":"10.1109/SBESC.2012.15","DOIUrl":"https://doi.org/10.1109/SBESC.2012.15","url":null,"abstract":"Language based protection and high-level language virtual machines (JVM, CLR) have solved many problems of portability and dependability. Development of operating systems with these characteristics for embedded systems could enjoy these benefits with the solution of basic problems related to resource consumption and performance. This paper presents the JingleOS, an operating system designed on these concepts for devices with a few kibibytes of RAM and 8 bits microcontrollers. To support the system design, advanced compiler techniques and extensions of the Java programming language were used, in order to allow low-level hardware access and bare metal execution.","PeriodicalId":112286,"journal":{"name":"2012 Brazilian Symposium on Computing System Engineering","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127264757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
SCProcessor Builder: A Tool to Create and Simulate Processors in SystemC SCProcessor Builder:在SystemC中创建和模拟处理器的工具
2012 Brazilian Symposium on Computing System Engineering Pub Date : 2012-11-05 DOI: 10.1109/SBESC.2012.54
J. Melo, Luiz Eduardo Cunha Leite, Max M. Silveira, Rivaldo Junior, M. Kreutz
{"title":"SCProcessor Builder: A Tool to Create and Simulate Processors in SystemC","authors":"J. Melo, Luiz Eduardo Cunha Leite, Max M. Silveira, Rivaldo Junior, M. Kreutz","doi":"10.1109/SBESC.2012.54","DOIUrl":"https://doi.org/10.1109/SBESC.2012.54","url":null,"abstract":"This paper presents the SCProcessor Builder that consists on a toolset that enables the modeling and simulation of different processor architecture and behavior. The models are designed using XML language and state machines for the structural and behavior parts respectively. The proposed tool converts the models to SystemC in order to simulate the execution of programs on modeled processors.","PeriodicalId":112286,"journal":{"name":"2012 Brazilian Symposium on Computing System Engineering","volume":"165 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123003221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Energy-Aware Technology-Based DVFS Mechanism for the Android Operating System 基于能量感知技术的Android操作系统DVFS机制
2012 Brazilian Symposium on Computing System Engineering Pub Date : 2012-11-05 DOI: 10.1109/SBESC.2012.43
A. Silva-Filho, P. Bezerra, F. Q. Silva, Antonio L. O. C. Junior, André L. M. Santos, P. Costa, R. Miranda
{"title":"Energy-Aware Technology-Based DVFS Mechanism for the Android Operating System","authors":"A. Silva-Filho, P. Bezerra, F. Q. Silva, Antonio L. O. C. Junior, André L. M. Santos, P. Costa, R. Miranda","doi":"10.1109/SBESC.2012.43","DOIUrl":"https://doi.org/10.1109/SBESC.2012.43","url":null,"abstract":"DVFS is an efficient energy saving technique for processors during program execution time. In this paper, we will focus efforts on 3G and Wi-Fi technologies to evaluate the impact of energy consumption when combined with DVFS mechanism based on the Android operating system. An experimental infrastructure with basis on Samsung's Smartphone was used to evaluate the proposed strategy to reduce energy consumption. Results of the proposed approach was compared with nonoptimized approach and an average reduction about 30% in terms of energy consumption was obtained when compared with performance mode.","PeriodicalId":112286,"journal":{"name":"2012 Brazilian Symposium on Computing System Engineering","volume":"386 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123250016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Schedulability Analysis of Sporadic Messages in the FlexRay Dynamic Segment FlexRay动态段中零星消息的可调度性分析
2012 Brazilian Symposium on Computing System Engineering Pub Date : 2012-11-05 DOI: 10.1109/SBESC.2012.35
R. Lange, R. S. Oliveira, Eduardo Bonet, F. Vasques
{"title":"Schedulability Analysis of Sporadic Messages in the FlexRay Dynamic Segment","authors":"R. Lange, R. S. Oliveira, Eduardo Bonet, F. Vasques","doi":"10.1109/SBESC.2012.35","DOIUrl":"https://doi.org/10.1109/SBESC.2012.35","url":null,"abstract":"FlexRay is a communication protocol heavily promoted as the future de facto standard for automotive systems. A major challenge associated with the design of FlexRay systems is the response time analysis of sporadic messages transmitted in the dynamic segment, a problem that has been shown to be a combinatorial problem. Although there are several methods available to make this analysis, they mainly rely on optimization techniques such as Integer Linear Programming (ILP), or use the Real-Time Calculus (RTC) framework. In this work we propose a method with pseudo-polynomial complexity to derive an upper bound for sporadic messages transmitted in the dynamic segment. We assess the performance of the proposed method comparing it with state-of-the-art methods available in the literature.","PeriodicalId":112286,"journal":{"name":"2012 Brazilian Symposium on Computing System Engineering","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114964936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Impact on Reliability in the Control-Flow of Programs under Compiler Optimizations 编译器优化对程序控制流可靠性的影响
2012 Brazilian Symposium on Computing System Engineering Pub Date : 2012-11-05 DOI: 10.1109/SBESC.2012.17
R. Parizi, R. Ferreira, Álvaro Freitas Moreira, L. Carro
{"title":"Impact on Reliability in the Control-Flow of Programs under Compiler Optimizations","authors":"R. Parizi, R. Ferreira, Álvaro Freitas Moreira, L. Carro","doi":"10.1109/SBESC.2012.17","DOIUrl":"https://doi.org/10.1109/SBESC.2012.17","url":null,"abstract":"This paper evaluates the impact on reliability in the control-flow of programs that compiler optimizations incur in terms of fault coverage for the Automatic Correction of Control-flow Errors technique. This technique was implemented in the LLVM framework, enabling the automated analysis of programs. In order to evaluate the efficiency of the technique of fault tolerance we performed a series of fault injection experiments using the MiBench benchmark suite as case study, measuring how individual and combined optimizations impact reliability.","PeriodicalId":112286,"journal":{"name":"2012 Brazilian Symposium on Computing System Engineering","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128351020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Power Reduction on Embedded Systems Achieved by a Synchronous Finite State Machine Design Technique 用同步有限状态机设计技术实现嵌入式系统的功耗降低
2012 Brazilian Symposium on Computing System Engineering Pub Date : 2012-11-05 DOI: 10.1109/SBESC.2012.22
D. Renaux, Fabiana Pöttker
{"title":"Power Reduction on Embedded Systems Achieved by a Synchronous Finite State Machine Design Technique","authors":"D. Renaux, Fabiana Pöttker","doi":"10.1109/SBESC.2012.22","DOIUrl":"https://doi.org/10.1109/SBESC.2012.22","url":null,"abstract":"Embedded applications that can be modeled as a Synchronous Finite State Machine are prone to a significant reduction in energy consumption when a very straightforward implementation approach is used. The potential for energy consumption reduction is highly dependent of the clock of the Synchronous Finite State Machine. Although the method is limited to synchronous FSM applications the benefits are worth the effort to attempt this modeling approach. The implementation requires only a timer (hardware timer or RTOS timer) that provides the clock of the Synchronous FSM. The energy reduction is obtained by changing the state of the processor to a low power state.","PeriodicalId":112286,"journal":{"name":"2012 Brazilian Symposium on Computing System Engineering","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130699734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
RAPTOR-Design: Refactorable Architecture Processor to Optimize Recurrent Design RAPTOR-Design:优化循环设计的可重构架构处理器
2012 Brazilian Symposium on Computing System Engineering Pub Date : 2012-11-05 DOI: 10.1109/SBESC.2012.55
Paulo Garcia, T. Gomes, F. Salgado, J. Cabral, J. Monteiro, A. Tavares
{"title":"RAPTOR-Design: Refactorable Architecture Processor to Optimize Recurrent Design","authors":"Paulo Garcia, T. Gomes, F. Salgado, J. Cabral, J. Monteiro, A. Tavares","doi":"10.1109/SBESC.2012.55","DOIUrl":"https://doi.org/10.1109/SBESC.2012.55","url":null,"abstract":"The growth in embedded systems complexity has created the demand for novel tools which allow rapid systems development and facilitate the designer's management of complexity. Especially since systems must incorporate a variety of often contradictory characteristics, achieving design metrics in short development time is an increasing challenge. This paper presents RAPTOR-Design, a framework for System-on-Chip (SoC) design which incorporates a customizable processor architecture and allows rapid software-to-hardware migration, custom hardware integration in a tightly-coupled fashion and seamless Fault Tolerance (FT) capabilities for FPGA platforms. Impact on design metrics of processor customization, FT-capabilities and custom hardware integration are presented, as well as an overview of the design process using RAPTOR-Design.","PeriodicalId":112286,"journal":{"name":"2012 Brazilian Symposium on Computing System Engineering","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114644743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信