Power Reduction on Embedded Systems Achieved by a Synchronous Finite State Machine Design Technique

Abstract

Embedded applications that can be modeled as a Synchronous Finite State Machine are prone to a significant reduction in energy consumption when a very straightforward implementation approach is used. The potential for energy consumption reduction is highly dependent of the clock of the Synchronous Finite State Machine. Although the method is limited to synchronous FSM applications the benefits are worth the effort to attempt this modeling approach. The implementation requires only a timer (hardware timer or RTOS timer) that provides the clock of the Synchronous FSM. The energy reduction is obtained by changing the state of the processor to a low power state.