2012 Brazilian Symposium on Computing System Engineering最新文献

Towards an Efficient Memory Architecture for Video Decoding Systems 面向视频解码系统的高效存储器结构研究

2012 Brazilian Symposium on Computing System Engineering Pub Date : 2012-11-05 DOI: 10.1109/SBESC.2012.45

A. Bonatto, M. Negreiros, A. Soares, A. Susin

{"title":"Towards an Efficient Memory Architecture for Video Decoding Systems","authors":"A. Bonatto, M. Negreiros, A. Soares, A. Susin","doi":"10.1109/SBESC.2012.45","DOIUrl":"https://doi.org/10.1109/SBESC.2012.45","url":null,"abstract":"Multimedia applications are known to use large amounts of memory. The video modules need also high throughput memory port for coding and decoding high resolution video sequences. The design of a multimedia System-on-Chip (SoC) could implement embedded block RAMs but it is much more cost-effective to use a single external memory at the expense of a multichannel memory controller. This paper presents the design and implementation of an efficient memory hierarchy for a Set-Top Box (STB) SoC with a video decoder. To use efficiently the Double Data Rate (DDR) external memory it must be accessed in burst mode whenever possible. In this paper we develop an analysis and implementation of a four level memory hierarchy targeting data latency reduction and bandwidth optimization of the memory port. The case study is DDR2 SDRAM memory used as the main system video memory in a digital television set-top box implemented on a Virtex-5 FPGA. This paper presents the architecture of the system and shows that the memory hierarchy efficiently uses the DDR characteristics while serving four client processes. The proposed memory architecture can reduce data latency in 78% when compared to a direct demand-access procedure.","PeriodicalId":112286,"journal":{"name":"2012 Brazilian Symposium on Computing System Engineering","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115304994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Design and Implementation of a Network Centric Appliance Platform 一个以网络为中心的设备平台的设计与实现

2012 Brazilian Symposium on Computing System Engineering Pub Date : 2012-11-05 DOI: 10.1109/SBESC.2012.46

D. Pasetto, H. Franke, K. Schleupen, David Maze, Hartmut Penner, Heather D. Achilles, Catherine H. Crawford, M. Purcell

{"title":"Design and Implementation of a Network Centric Appliance Platform","authors":"D. Pasetto, H. Franke, K. Schleupen, David Maze, Hartmut Penner, Heather D. Achilles, Catherine H. Crawford, M. Purcell","doi":"10.1109/SBESC.2012.46","DOIUrl":"https://doi.org/10.1109/SBESC.2012.46","url":null,"abstract":"Increasing demands on end-to-end solution performance has lead to a generation of workload optimized systems and appliances, with tightly integrated hardware and software delivering substantial improvements over general purpose architectures. Among the many challenges encountered in designing an appliance, the most complex one is making hardware and software high performance and, at the same time, render the system versatile enough to support as many workloads as possible. This paper provides a high level overview of the design and implementation process of such an appliance architecture, as realized by the IBM PowerEN team. The platform includes new silicon (the PowerEN processor), a novel system level board (Chroma card), system software and development kit, as well as end user applications for different industry domains. The solution has been completely designed by the team, starting from concept, to architecture, to implementation and delivery. The paper describes the most important characteristics of the platform, detailing how these influence its capability of supporting multiple optimized workloads.","PeriodicalId":112286,"journal":{"name":"2012 Brazilian Symposium on Computing System Engineering","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127177748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Cache Preemption Related Delay Accounting via Static Analysis and Functional Simulation 通过静态分析和功能仿真计算缓存抢占相关延迟

2012 Brazilian Symposium on Computing System Engineering Pub Date : 2012-11-05 DOI: 10.1109/SBESC.2012.36

R. A. Starke, R. S. Oliveira

引用次数: 0

SICXE: Improving Experience with Didactic Processors SICXE:提高教学处理器的体验

2012 Brazilian Symposium on Computing System Engineering Pub Date : 2012-11-05 DOI: 10.1109/SBESC.2012.24

Raimundo Valter Costa, Silvio Fernandes, Leonardo Casilo, A. Soares, Denis Freire

引用次数: 3

A Model to Calculate Exact End-to-End Delay of Sporadic Flows on AFDX Network Using Mathematical Programming 基于数学规划的AFDX网络零星流端到端精确延迟计算模型

2012 Brazilian Symposium on Computing System Engineering Pub Date : 2012-11-05 DOI: 10.1109/SBESC.2012.25

Leonardo Malta, R. S. Oliveira

引用次数: 1

A Methodology to Adapt Data Path Architectures to a MIPS-1 Model 一种使数据路径体系结构适应MIPS-1模型的方法

2012 Brazilian Symposium on Computing System Engineering Pub Date : 2012-11-05 DOI: 10.1109/SBESC.2012.41

L. A. Casillo, Ivan Saraiva Silva

引用次数: 1

Partitioning Algorithms Analysis for Heterogeneous NoC Based MPSoC 基于异构NoC的MPSoC分区算法分析

2012 Brazilian Symposium on Computing System Engineering Pub Date : 2012-11-05 DOI: 10.1109/SBESC.2012.42

Igor K. Pinotti, T. Webber, Natanael Ribeiro, Carlos N. Fraga, R. Fagundes, C. Marcon

引用次数: 1

Device to Assist the Visually Impaired in Reading Printed or Scanned Documents 协助视障人士阅读打印或扫描文件的装置

2012 Brazilian Symposium on Computing System Engineering Pub Date : 2012-11-05 DOI: 10.1109/SBESC.2012.14

Luis Coutinho, A. M. Girao, J. B. Frota, Elias Teodoro da Silva

引用次数: 4

A Comprehensive Complexity Analysis of User-Level Memory Allocator Algorithms 用户级内存分配算法的综合复杂性分析

2012 Brazilian Symposium on Computing System Engineering Pub Date : 2012-11-05 DOI: 10.1109/SBESC.2012.27

T. Ferreira, M. Fernandes, Rivalino Matias

引用次数: 5

Request Batching Self-Configuration in Byzantine Fault-Tolerant Replication 拜占庭容错复制中的请求批处理自配置

2012 Brazilian Symposium on Computing System Engineering Pub Date : 2012-11-05 DOI: 10.1109/SBESC.2012.32

A. S. Sá, A. E. S. Freitas, R. Macêdo

{"title":"Request Batching Self-Configuration in Byzantine Fault-Tolerant Replication","authors":"A. S. Sá, A. E. S. Freitas, R. Macêdo","doi":"10.1109/SBESC.2012.32","DOIUrl":"https://doi.org/10.1109/SBESC.2012.32","url":null,"abstract":"Replication techniques that tolerate byzantine failures have been applied in distributed computing to cope with hostile environments in which system components may fail due to malicious or natural causes (e.g., intrusions). From the seminal work of Lamport, Pease and Shostak on Byzantine Generals, in 1982, Castro and Liskov proposed in 1999 a successful solution, named PBFT, which overcomes performance drawbacks of previous ones, based on a number of protocol optimizations, including the use of request batching. Such a work motivated several other works as extension of the PBFT protocol, improving PBFT performance in certain computing environment conditions. In these solutions, which we call PBFT-family protocols, the tuning of the request batching parameters are realized in design time. However, such configuration may not yield the desired performance in dynamic distributed systems where the underlying characteristics change dynamically (e.g., workload, channel QoS, network topology, etc.). To answer to this challenge, this paper proposes an innovative solution to the dynamic configuration of batching parameters inspired on feedback control theory. In order to evaluate its efficiency, the proposed solution is simulated in various scenarios and compared with the original version used in the PBFT-family protocols.","PeriodicalId":112286,"journal":{"name":"2012 Brazilian Symposium on Computing System Engineering","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133316300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2