Raimundo Valter Costa, Silvio Fernandes, Leonardo Casilo, A. Soares, Denis Freire
{"title":"SICXE: Improving Experience with Didactic Processors","authors":"Raimundo Valter Costa, Silvio Fernandes, Leonardo Casilo, A. Soares, Denis Freire","doi":"10.1109/SBESC.2012.24","DOIUrl":null,"url":null,"abstract":"This paper presents the design, hardware description and test of SICXE processor, as well as a development environment and simulation tools for this architecture. Based on SIC processor, SICXE is a didactic 32-bit RISC that offers integer ALU, floating-point ALU, interrupts, addressing up to 4GB of program memory, programmed I/O based, DMA-based I/O and also supports a simple operating system. The physical model proposed fit in a compact design, operating at frequencies above 50 MHz and may compose larger projects of embedded systems. This entire software and hardware environment also may be applied for university courses in disciplines such as computer architecture, operating systems, system software and compilers.","PeriodicalId":112286,"journal":{"name":"2012 Brazilian Symposium on Computing System Engineering","volume":"70 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 Brazilian Symposium on Computing System Engineering","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SBESC.2012.24","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
This paper presents the design, hardware description and test of SICXE processor, as well as a development environment and simulation tools for this architecture. Based on SIC processor, SICXE is a didactic 32-bit RISC that offers integer ALU, floating-point ALU, interrupts, addressing up to 4GB of program memory, programmed I/O based, DMA-based I/O and also supports a simple operating system. The physical model proposed fit in a compact design, operating at frequencies above 50 MHz and may compose larger projects of embedded systems. This entire software and hardware environment also may be applied for university courses in disciplines such as computer architecture, operating systems, system software and compilers.