2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE)最新文献

Perturb and Observe (P&O) based MPPT controller for PV connected brushless DC motor drive 基于摄动和观察(P&O)的PV连接无刷直流电机驱动MPPT控制器

2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE) Pub Date : 2017-12-14 DOI: 10.1109/ICEICE.2017.8191877

G. Kanagachidambaresan, R. Anand, Akhtar Kalam

引用次数: 7

Design of smart meter for smart grid application through true time — MATLAB 设计智能电表，实现智能电网的实时应用

2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE) Pub Date : 2017-04-27 DOI: 10.1109/ICEICE.2017.8191846

R. Anand, G. R. Kanagachidambaresan, M. Balaji, K.S. Chandragupta Mauryan

引用次数: 2

Design and analysis of FPGA based 32 bit ALU using reversible gates 基于FPGA的32位可逆门ALU设计与分析

2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE) Pub Date : 2017-04-27 DOI: 10.1109/ICEICE.2017.8191959

S. Swamynathan, V. Banumathi

{"title":"Design and analysis of FPGA based 32 bit ALU using reversible gates","authors":"S. Swamynathan, V. Banumathi","doi":"10.1109/ICEICE.2017.8191959","DOIUrl":"https://doi.org/10.1109/ICEICE.2017.8191959","url":null,"abstract":"An Arithmetic logic Unit (ALU) is used in arithmetic, logical function in all processor. It is also an important subsystem in digital system design. Arithmetic Logic Unit (ALU) is one of the most important components of any system and is used in many appliances like calculators, cell phones, and computers. A 32-bit ALU was designed using Verilog HDL with the logical gates such as AND and OR for each one bit ALU circuit. The design was implemented in Xilinx. It can work fast than the ALU processor using less power. The design of an ALU and a Cache memory for use in a high performance processor was examined. Reversible logic vital in recent years because it has ability to reduce the power dissipation which is main requirement in low power design. ALU which are designed using non reversible logic gates consume more power. So there is a need for lesser power consumption and the reversible logic has been playing vital role during recent years for low power VLSI Design techniques. This technique helps in reducing power consumption and power dissipation. This paper presents an implementation of ALU based on reversible logic while comparing it to an ALU architecture with the normal logic gates. All the modules are simulated in modelsim SE 6.4c and synthesised using Xilinx ISE 14.5. ALU which is designed using non reversible logic gates consume more power of about 0.312 mw and the implementation of ALU based on reversible logic reduces the power consumption during operations to about 5.1 percentages.","PeriodicalId":110529,"journal":{"name":"2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE)","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124584175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Fault tolerant improvement mechanism for 3D memories using built-in self repair scheme 采用内置自修复方案的三维存储器容错改进机制

2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE) Pub Date : 2017-04-27 DOI: 10.1109/ICEICE.2017.8192446

P. Sivakumar, G. Karthy, K. V. Bharani

{"title":"Fault tolerant improvement mechanism for 3D memories using built-in self repair scheme","authors":"P. Sivakumar, G. Karthy, K. V. Bharani","doi":"10.1109/ICEICE.2017.8192446","DOIUrl":"https://doi.org/10.1109/ICEICE.2017.8192446","url":null,"abstract":"An efficient BISR technique is proposed to find an optimum point of performance scheme is proposed for 2D and 3D memories. Fault Tolerant Improvement Mechanism is provided for all memories using Built-In Self-Test (March Test Algorithm) which figure out the memory faults, total number of faults, and irreparability and test the memories simultaneously. Using LFSR architecture the transistor is reduced. After all memories are tested, only faulty memories are sequentially tested and the shared BIRA repaired the fault according to the sizes of memories in descending order to obtain the fast test and repair with low area overhead. Circuit design is created using LFSR architecture that reduces the flipflop level which leads to reduce the time. The detected faults are send to the BIST, then the BIST sends the faults to the BIRA module which uses Cresta for repair analysis and sends the solution. Three number of spare rows & columns are added along with 2 sub analyzers are used to accomplish a fast analysis speed, and an optimal repair rate for every different possible combinations of spare rows & columns.","PeriodicalId":110529,"journal":{"name":"2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125556822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Optimal placement of static VAR compensator (SVC) in power system along with wind power generation 静态无功补偿器(SVC)在风电系统中的优化配置

2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE) Pub Date : 2017-04-01 DOI: 10.1109/ICEICE.2017.8191951

T. Srikanth, S. Selvi, V. Pushya

{"title":"Optimal placement of static VAR compensator (SVC) in power system along with wind power generation","authors":"T. Srikanth, S. Selvi, V. Pushya","doi":"10.1109/ICEICE.2017.8191951","DOIUrl":"https://doi.org/10.1109/ICEICE.2017.8191951","url":null,"abstract":"Power system is nothing but a power Generation, power Transmission and power Distribution. Most of the conventional energy sources generate the power at the hill areas or at the longer distances from electrical consumers, so that an electrical transmission and distribution system plays a vital role in power system. Since most of the electrical loads are inductive loads and transmission and distribution lines itself not pure resistive lines, there is a reactive power requirement in the transmission and distribution systems. If transmission and distribution lines are not maintaining the required reactive power limits, then power losses increase and it also effect on the stability. There are different types of sources available for reactive power management in the power system are shunt capacitors, synchronous condensers and Static Var compensator (SVC). In this paper, optimal placement of SVC in transmission and distribution lines along with Distributed Generation sources (DGS) is analyzed based on better reactive support and stability limits in the lines.","PeriodicalId":110529,"journal":{"name":"2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115445401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Autonomous congestion control deploying SAURP 自动拥塞控制部署SAURP

2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE) Pub Date : 2017-04-01 DOI: 10.1109/ICEICE.2017.8191874

D. Bell, D. Asir

引用次数: 0

Study of radiation patterns of circular patch antenna at different modes 圆形贴片天线在不同模式下的辐射方向图研究

2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE) Pub Date : 2017-04-01 DOI: 10.1109/ICEICE.2017.8192445

Vidushi Mahalwar, Y. Choukiker

引用次数: 1

Error detection and correction using decimal matrix code: Survey 使用十进制矩阵码的错误检测和纠正:调查

2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE) Pub Date : 2017-04-01 DOI: 10.1109/ICEICE.2017.8191867

T. E. Santhia, R. Bharathi, M. Revathy

引用次数: 2

Characteristic mode analysis of mobile hand held device for MIMO applications 用于MIMO应用的移动手持设备特征模式分析

2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE) Pub Date : 2017-04-01 DOI: 10.1109/ICEICE.2017.8191841

Abhishek Pandiya, Y. Choukiker

引用次数: 0

Power oscillation damping using ultracapcitor and voltage source based FACTS controllers 利用超级电容器和基于电压源的FACTS控制器进行功率振荡阻尼

2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE) Pub Date : 2017-04-01 DOI: 10.1109/ICEICE.2017.8191878

Kantilal Dayalal Joshi, V. Chandrakar

引用次数: 1