Fault tolerant improvement mechanism for 3D memories using built-in self repair scheme

Abstract

An efficient BISR technique is proposed to find an optimum point of performance scheme is proposed for 2D and 3D memories. Fault Tolerant Improvement Mechanism is provided for all memories using Built-In Self-Test (March Test Algorithm) which figure out the memory faults, total number of faults, and irreparability and test the memories simultaneously. Using LFSR architecture the transistor is reduced. After all memories are tested, only faulty memories are sequentially tested and the shared BIRA repaired the fault according to the sizes of memories in descending order to obtain the fast test and repair with low area overhead. Circuit design is created using LFSR architecture that reduces the flipflop level which leads to reduce the time. The detected faults are send to the BIST, then the BIST sends the faults to the BIRA module which uses Cresta for repair analysis and sends the solution. Three number of spare rows & columns are added along with 2 sub analyzers are used to accomplish a fast analysis speed, and an optimal repair rate for every different possible combinations of spare rows & columns.