Error detection and correction using decimal matrix code: Survey

Abstract

Scaling of CMOS technology to nanoscale increases soft error rate in memory cells. Both single bit upset and Multiple Cell Upsets (MCUs) causes reliability issues in memory applications. Transient multiple cell upsets (MCUs) are becoming major issues in the reliability of memories exposed to radiation environment and affect large number of cells. Hence to provide fault tolerant memory cells, Error detection and Correction Codes are used which are being discussed here in this paper.