Design and analysis of FPGA based 32 bit ALU using reversible gates

Abstract

An Arithmetic logic Unit (ALU) is used in arithmetic, logical function in all processor. It is also an important subsystem in digital system design. Arithmetic Logic Unit (ALU) is one of the most important components of any system and is used in many appliances like calculators, cell phones, and computers. A 32-bit ALU was designed using Verilog HDL with the logical gates such as AND and OR for each one bit ALU circuit. The design was implemented in Xilinx. It can work fast than the ALU processor using less power. The design of an ALU and a Cache memory for use in a high performance processor was examined. Reversible logic vital in recent years because it has ability to reduce the power dissipation which is main requirement in low power design. ALU which are designed using non reversible logic gates consume more power. So there is a need for lesser power consumption and the reversible logic has been playing vital role during recent years for low power VLSI Design techniques. This technique helps in reducing power consumption and power dissipation. This paper presents an implementation of ALU based on reversible logic while comparing it to an ALU architecture with the normal logic gates. All the modules are simulated in modelsim SE 6.4c and synthesised using Xilinx ISE 14.5. ALU which is designed using non reversible logic gates consume more power of about 0.312 mw and the implementation of ALU based on reversible logic reduces the power consumption during operations to about 5.1 percentages.