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2008 International Conference on Electronic Design最新文献

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Real-time face detection/identification for surveillance system 实时人脸检测/识别监控系统
2008 International Conference on Electronic Design Pub Date : 2008-12-01 DOI: 10.1109/ICED.2008.4786776
N. Suvonvorn, A. Chocksuriwong
{"title":"Real-time face detection/identification for surveillance system","authors":"N. Suvonvorn, A. Chocksuriwong","doi":"10.1109/ICED.2008.4786776","DOIUrl":"https://doi.org/10.1109/ICED.2008.4786776","url":null,"abstract":"Face processing is one among the popular problems of detection and recognition. In surveillance system application, the massive data of video is analyzed by complex algorithms that must consider the real-time constraints. In this paper we propose a face processing framework as a component-based architecture for dealing with face online processing. Face detection and classification algorithms are realized based on a Haar-like features and support vector machine (SVM) respectively as a way to efficiently extract a face image and enhance face recognition rates with robustness on different orientation Experimental results are presented with discussion.","PeriodicalId":103889,"journal":{"name":"2008 International Conference on Electronic Design","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131271736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A portable network traffic analyzer 便携式网络流量分析器
2008 International Conference on Electronic Design Pub Date : 2008-12-01 DOI: 10.1109/ICED.2008.4786787
M. Rahman, Z. Khalib, R. B. Ahmad
{"title":"A portable network traffic analyzer","authors":"M. Rahman, Z. Khalib, R. B. Ahmad","doi":"10.1109/ICED.2008.4786787","DOIUrl":"https://doi.org/10.1109/ICED.2008.4786787","url":null,"abstract":"Embedded system is known for its limitation in terms of processing power, memory, and power consumption. Incorporating solution into an embedded system, which requires optimum usage of these limitation, is thus a challenge. The aim of this study is to see how Embedded Linux could cope with those limitations in producing reliable embedded web-based traffic monitoring system. The approach to the study is to adopt a low-end embedded Linux platform and develop a network traffic monitoring system which runs on the platform. Among the functionalities incorporated include capturing and storing network packet information into files, analyzing data statistically and displaying minimal statistical data as well as sending data files through TCP/IP connection to the web based monitoring system. This paper will describe the architectural design and implementation of the network monitoring system. Interesting enough the system proved to be competent, where it manages to provide useful reliable information within its limitation.","PeriodicalId":103889,"journal":{"name":"2008 International Conference on Electronic Design","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134584331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Implementing image processing algorithms using ‘Hardware in the loop’ approach for Xilinx FPGA 在Xilinx FPGA上使用“硬件在循环”方法实现图像处理算法
2008 International Conference on Electronic Design Pub Date : 2008-12-01 DOI: 10.1109/ICED.2008.4786653
M. Kiran, Kan Mei War, Lim Mei Kuan, Liang Kim Meng, L. W. Kin
{"title":"Implementing image processing algorithms using ‘Hardware in the loop’ approach for Xilinx FPGA","authors":"M. Kiran, Kan Mei War, Lim Mei Kuan, Liang Kim Meng, L. W. Kin","doi":"10.1109/ICED.2008.4786653","DOIUrl":"https://doi.org/10.1109/ICED.2008.4786653","url":null,"abstract":"This paper outlines the investigation conducted in fine tuning the performance of our automated surveillance system. The constituent components of the system must have a processing speed of less than 40 ms. This is usually considered to be a standard timing constraint for most automated surveillance systems. To meet this constraint, it is important to quantify the reduction in processing speed that can be achieved if a component of the surveillance system is embedded onto a hardware based platform like an FPGA. A benchmark study was conducted to identify the component that contributed to the longest processing time in the entire system. Once the offending component was identified, its functionality was embedded onto the FPGA board using a combination of MATLAB-Simulink and Xilinx system generator prototyping environment. The results obtained indicated that the processing speed of the component was constantly faster on the FPGA platform as compared to MATLAB or C++ environment.","PeriodicalId":103889,"journal":{"name":"2008 International Conference on Electronic Design","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130511128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Design methodology to achieve good testability of VLSI chips: An industrial perspective 实现VLSI芯片良好可测试性的设计方法:工业视角
2008 International Conference on Electronic Design Pub Date : 2008-12-01 DOI: 10.1109/ICED.2008.4786782
H. Lo, W. Lee, M. Reaz, N. Hisham, A. Shakaff
{"title":"Design methodology to achieve good testability of VLSI chips: An industrial perspective","authors":"H. Lo, W. Lee, M. Reaz, N. Hisham, A. Shakaff","doi":"10.1109/ICED.2008.4786782","DOIUrl":"https://doi.org/10.1109/ICED.2008.4786782","url":null,"abstract":"Many of today's very large scale integration (VLSI) chips are digital design that has hundreds of thousands to millions of transistors per chip. Testing of such large VLSI chips proves to be a challenge. One method of addressing this challenge is the introduction of design for test (DFT) features into the VLSI chips. This paper describes an efficient methodology of achieving good testability of VLSI chip using a combination of register transfer level (RTL) coding styles with full scan chain implementation and automatic test pattern generation (ATPG). This paper also describes the method of sharing of DFT pins associated with scan chain in order to reduce packaging cost due to DFT.","PeriodicalId":103889,"journal":{"name":"2008 International Conference on Electronic Design","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122294941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Implementation of SHA-2 hash function for a digital signature System-on-Chip in FPGA 片上系统数字签名SHA-2哈希函数的FPGA实现
2008 International Conference on Electronic Design Pub Date : 2008-12-01 DOI: 10.1109/ICED.2008.4786681
M. Khalil, M. Nazrin, Y. Hau
{"title":"Implementation of SHA-2 hash function for a digital signature System-on-Chip in FPGA","authors":"M. Khalil, M. Nazrin, Y. Hau","doi":"10.1109/ICED.2008.4786681","DOIUrl":"https://doi.org/10.1109/ICED.2008.4786681","url":null,"abstract":"The widespread adoption of Internet as a secure medium for communication and e-commerce has made cryptography a vital part of today's information systems. However, to achieve a more pervasive deployment, the supporting cryptographic (crypto) systems should exhibit processing power of high performance and efficiency. These demanding requirements can be achieved by integrating the cryptosystems into designs based on System-on-Chip (SoC). In this paper, the design and implementation of a crypto hash SHA-2 logic core in reconfigurable hardware is presented. We also discuss a public-key crypto SoC, which uses the SHA-2 hash core in conjunction with a 2048-bit RSA co-processor to perform a digital signature security scheme. We use Verilog to model the hardware, and C to code the embedded software. With the crypto SoC implemented in an Altera Nios II Stratix FPGA-based prototyping system running on a 50 MHz system clock, we obtained a throughput of 644 Mbits/sec for our SHA-512 hardware core.","PeriodicalId":103889,"journal":{"name":"2008 International Conference on Electronic Design","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123713199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Considerations of performance factors in CMOS designs CMOS设计中性能因素的考虑
2008 International Conference on Electronic Design Pub Date : 2008-12-01 DOI: 10.1109/ICED.2008.4786783
S. Govindarajulu, T. Prasad
{"title":"Considerations of performance factors in CMOS designs","authors":"S. Govindarajulu, T. Prasad","doi":"10.1109/ICED.2008.4786783","DOIUrl":"https://doi.org/10.1109/ICED.2008.4786783","url":null,"abstract":"Recently, designers have been using the energy-delay product (EDP) as a metric of goodness for CMOS designs due to certain perceived shortcomings of the more traditional power-delay product (PDP). As the industry moves to deep sub-micron technology, it is appropriate to investigate existing design metrics. In this work, we investigated the performance metrics, and generalized set of metrics are proposed. Supply voltage (VDD) and threshold voltage (VT) scaling are two popular approaches to power reduction. We analyzed their effects on power and frequency and search for feasible region of operation. The relationship between the optimal operating points and generalized design metrics is established. We present some new insights in power considerations of deep submicron CMOS designs. We compared EDP with PDP and introduced a new metric called power-energy product (PEP). Comparing the three metrics, it is observed that EDP places a higher weight on delay reduction, PEP places a higher weight on power reduction, and PDP tries to strike a balance between the two.","PeriodicalId":103889,"journal":{"name":"2008 International Conference on Electronic Design","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115995939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Synthesis techniques for implementation of wave-pipelined circuits in ASICs 在asic中实现波管道电路的合成技术
2008 International Conference on Electronic Design Pub Date : 2008-12-01 DOI: 10.1109/ICED.2008.4786670
V. Vireen, G. Seetharaman, B. Venkataramani
{"title":"Synthesis techniques for implementation of wave-pipelined circuits in ASICs","authors":"V. Vireen, G. Seetharaman, B. Venkataramani","doi":"10.1109/ICED.2008.4786670","DOIUrl":"https://doi.org/10.1109/ICED.2008.4786670","url":null,"abstract":"Higher operating frequencies may be obtained in digital systems by using wave-pipelining which permits clock frequencies higher that dictated by largest propagation delay between input and output. This, however, requires proper selection of clock periods and clock skews so as to latch the output of combinational logic circuits at the stable periods. In the literature, only trial and error and manual procedures are adopted for these selections. The major contribution of this paper is the proposal for three schemes for synthesis of wave-pipelined circuits using commercially available synthesis tools. To test the efficacy of the proposed schemes, an 8-bit ripple carry is implemented by adopting three schemes: wave-pipelining, pipelining and non-pipelining. From the implementation results, it is observed that the wave pipelined circuit is 2.8 times faster than the non pipelined circuit at the cost of increase in area by a factor of 1.8. The wave pipelined circuit 3.5% faster compared to pipelined circuit and requires 8.7% less area over pipelined circuit.","PeriodicalId":103889,"journal":{"name":"2008 International Conference on Electronic Design","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117300982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Link availability estimation for routing metrics in MANETs : An overview manet中路由度量的链路可用性估计:概述
2008 International Conference on Electronic Design Pub Date : 2008-12-01 DOI: 10.1109/ICED.2008.4786686
N.Z. Ali, R. B. Ahmad, S. Aljunid
{"title":"Link availability estimation for routing metrics in MANETs : An overview","authors":"N.Z. Ali, R. B. Ahmad, S. Aljunid","doi":"10.1109/ICED.2008.4786686","DOIUrl":"https://doi.org/10.1109/ICED.2008.4786686","url":null,"abstract":"A mobile ad hoc network (MANET) is a collection of wireless mobile terminals that are able to dynamically form a temporary network without any aid from fixed infrastructure or centralized administration. MANETs are strongly impacted by the mobility of the ad hoc nodes. Path broken, which is caused by node mobility , leads to the rerouting operations and the degradation of network performance. One critical issue for routing in MANETs is how to select reliable path that can last as long as possible. This paper will address the previous study on how to measure link availability or reliability in order to find more reliable paths. To solve this problem, a criterion that can judge the link reliability is needed. The metric for routing selection in terms of path availability which is based on link availability can be used to select reliable path.","PeriodicalId":103889,"journal":{"name":"2008 International Conference on Electronic Design","volume":"111 17","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120826093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Revolute control techniques of USBM simplified model USBM简化模型的旋转控制技术
2008 International Conference on Electronic Design Pub Date : 2008-12-01 DOI: 10.1109/ICED.2008.4786649
M. Ahmad, A. Nasir, M. S. Najib, M. S. Ramli, R. Samin, H. Ishak, N. Ghani
{"title":"Revolute control techniques of USBM simplified model","authors":"M. Ahmad, A. Nasir, M. S. Najib, M. S. Ramli, R. Samin, H. Ishak, N. Ghani","doi":"10.1109/ICED.2008.4786649","DOIUrl":"https://doi.org/10.1109/ICED.2008.4786649","url":null,"abstract":"Universal stretch and bending machine (USBM) is a combination of stretch machine and bending machine which are used in car door sash production. The main purpose of combining these two machines is to reduce the number of machines, space utilization and increase productivity. This paper presents the design and modeling for revolute control techniques of USBM simplified module. Conventional proportional-integral-derivative (PID), linear quadratic regulator (LQR), and proportional-derivative (PD)-type fuzzy logic controller (FLC) are proposed to control the angular position of the revolute model. Simulation is implemented in SIMULINK/MATLAB and the results of the response of the system with the controllers are presented in time domains. The performances of the control schemes are assessed in terms of input tracking capability and time response specifications. Finally, a comparative assessment of the control techniques is presented and discussed.","PeriodicalId":103889,"journal":{"name":"2008 International Conference on Electronic Design","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121439748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Micro Genetic Algorithm application in block transmission systems 微遗传算法在分组传输系统中的应用
2008 International Conference on Electronic Design Pub Date : 2008-12-01 DOI: 10.1109/ICED.2008.4786667
S. Babu, F. Ghani, Fadzli Mohd Salleh
{"title":"Micro Genetic Algorithm application in block transmission systems","authors":"S. Babu, F. Ghani, Fadzli Mohd Salleh","doi":"10.1109/ICED.2008.4786667","DOIUrl":"https://doi.org/10.1109/ICED.2008.4786667","url":null,"abstract":"Block transmission systems are used in inter symbol interference (ISI) channels for high data rate communication. In this system, messages are sent as blocks separated by known symbols. Detectors employing block-by-block detection basis is the optimum system and it can be implemented with global search techniques. The performance of such system is found better than block linear equalizers, block decision feedback equalizer. This paper presents the practical difficulty of such system and proposes usage of micro genetic algorithms as an alternative. The performance in terms of bit error rate is evaluated for channels with spectral nulls and hardware complexity is compared with present systems.","PeriodicalId":103889,"journal":{"name":"2008 International Conference on Electronic Design","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125495003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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