Synthesis techniques for implementation of wave-pipelined circuits in ASICs

Abstract

Higher operating frequencies may be obtained in digital systems by using wave-pipelining which permits clock frequencies higher that dictated by largest propagation delay between input and output. This, however, requires proper selection of clock periods and clock skews so as to latch the output of combinational logic circuits at the stable periods. In the literature, only trial and error and manual procedures are adopted for these selections. The major contribution of this paper is the proposal for three schemes for synthesis of wave-pipelined circuits using commercially available synthesis tools. To test the efficacy of the proposed schemes, an 8-bit ripple carry is implemented by adopting three schemes: wave-pipelining, pipelining and non-pipelining. From the implementation results, it is observed that the wave pipelined circuit is 2.8 times faster than the non pipelined circuit at the cost of increase in area by a factor of 1.8. The wave pipelined circuit 3.5% faster compared to pipelined circuit and requires 8.7% less area over pipelined circuit.