2008 International Conference on Electronic Design最新文献_第7页

A tightly coupled finite field arithmetic hardware in an FPGA-based embedded processor core for elliptic curve cryptography 椭圆曲线密码学中基于fpga嵌入式处理器核心的紧耦合有限域算法硬件

2008 International Conference on Electronic Design Pub Date : 2008-12-01 DOI: 10.1504/IJICT.2009.026430

M. Khalil-Hani, Arif Irwansyah, Y. Hau

{"title":"A tightly coupled finite field arithmetic hardware in an FPGA-based embedded processor core for elliptic curve cryptography","authors":"M. Khalil-Hani, Arif Irwansyah, Y. Hau","doi":"10.1504/IJICT.2009.026430","DOIUrl":"https://doi.org/10.1504/IJICT.2009.026430","url":null,"abstract":"This work presents the implementation of a tightly-coupled hardware architectural enhancement to the Altera FPGA-based Nios II embedded processor. The goal is to accelerate finite field arithmetic operations in the binary fields of F2 163 and F2 193, for application in a high-performance embedded system implementing elliptic-curve cryptography (ECC). The concept is to augment the embedded processor with a few custom instructions for fast finite field arithmetic operations. Instead of a co-processor, hardware acceleration of the arithmetic operation is provided by custom logic tightly coupled to the processor core and directly controlled by the instruction stream. This concept, which may be considered as a hardware-software codesign approach, is evaluated by prototyping an elliptic curve cryptosystem (ECC) on an Altera Stratix FPGA development board. Experimental results show that for the point multiplication operation, which is the core operation in an ECC computation, the implementation with custom instructions and tightly-coupled hardware is about 50% faster than the coprocessor based hardware.","PeriodicalId":103889,"journal":{"name":"2008 International Conference on Electronic Design","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132589541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Design and implementation of Wireless Biomedical Sensor Networks for ECG home health monitoring 用于心电家庭健康监测的无线生物医学传感器网络设计与实现

2008 International Conference on Electronic Design Pub Date : 2008-12-01 DOI: 10.1109/ICED.2008.4786688

R. Rashid, M. Rahim, M. Sarijari, N. Mahalin

引用次数: 20

Model reference adaptive control with Adaptive Parametric Black Box Controller 自适应参数黑盒控制器的模型参考自适应控制

2008 International Conference on Electronic Design Pub Date : 2008-12-01 DOI: 10.1109/ICED.2008.4786738

N. Ahmed, M. Y. Mashor, A. H. Adom

引用次数: 0

A novel economical duty cycle division multiplexing with electrical multiplexer and demultiplexer for optical communication systems 用于光通信系统的一种新型的、经济的、具有电复用器和解复用器的占空比分复用

2008 International Conference on Electronic Design Pub Date : 2008-12-01 DOI: 10.1504/IJICT.2009.026427

G. Mahdiraji, A. M. Mohammadi, A. Abas, M. Mokhtar, M. Abdullah

{"title":"A novel economical duty cycle division multiplexing with electrical multiplexer and demultiplexer for optical communication systems","authors":"G. Mahdiraji, A. M. Mohammadi, A. Abas, M. Mokhtar, M. Abdullah","doi":"10.1504/IJICT.2009.026427","DOIUrl":"https://doi.org/10.1504/IJICT.2009.026427","url":null,"abstract":"A duty cycle division multiplexing (DCDM) is proposed as an alternative multiplexing technique. It can be applied in either wired or wireless communication systems, although the focus in this paper is in optical fiber communications. The channel multiplexing and demultiplexing is performed electrically at single user bit rate which is very economic. In this paper, we examine 3 channels each operating at 10 Gb/s over a single optical carrier. The performance comparison is made against return-to-zero (RZ) transmitted pulses. Back-to-back receiver sensitivity and required optical signal-to-noise ratio (OSNR) of this system are examined and compared with 10 Gb/s RZ pulses. Effect of the chromatic dispersion is tested for DCDM channels and compared with 30 Gb/s RZ coding at the same transmission power. Also, the launched power of these two techniques is measured against system dispersion at BER of 10-9. The results show that, DCDM can support higher amount of chromatic dispersion than that RZ technique. In the end, receiver sensitivity and OSNR of 3-channel DCDM is tested at different bit rate of 2.5, 10, 25 and 40 Gb/s. A receiver sensitivity and OSNR of -16.8 dBm and 34.6 dB is required for the worst DCDM user when the system running at 3 times 40 Gb/s respectively.","PeriodicalId":103889,"journal":{"name":"2008 International Conference on Electronic Design","volume":"263 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126053002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

A parametric study of broadband Planar Inverted F antenna (PIFA) for WLAN application 无线局域网宽带平面倒F天线(PIFA)的参数化研究

2008 International Conference on Electronic Design Pub Date : 2008-12-01 DOI: 10.1109/ICED.2008.4786690

A. Azremi, N. A. Saidatul, R. Ahmad, P. Soh

引用次数: 17

Design of 12-bit, 1.8V current steering digital-to-analog converter 12位1.8V电流转向数模转换器的设计

2008 International Conference on Electronic Design Pub Date : 2008-12-01 DOI: 10.1109/ICED.2008.4786676

B. Naik, R. Rao, P. Chandrasekhar

引用次数: 0

Design of Embedded System for Grid Handtop Computing (ESGHC) 网格掌上计算嵌入式系统的设计

2008 International Conference on Electronic Design Pub Date : 2008-12-01 DOI: 10.1109/ICED.2008.4786756

L. Yong, Wongok Lee, M. A. Osman, C. Yong

引用次数: 0

Extraction of head and hand gesture features for recognition of sign language 基于头部和手部特征的手语识别

2008 International Conference on Electronic Design Pub Date : 2008-12-01 DOI: 10.1109/ICED.2008.4786633

Sazali Yaacob, H. Desa, Wan Mohd Ridzuan Wan Ab Majid

引用次数: 48

ASIC implementation of self tuned wave-pipelined circuits ASIC实现自调谐波管电路

2008 International Conference on Electronic Design Pub Date : 2008-12-01 DOI: 10.1109/ICED.2008.4786695

N. Venugopalachary, V. Vireen, G. Seetharaman, B. Venkataramani

{"title":"ASIC implementation of self tuned wave-pipelined circuits","authors":"N. Venugopalachary, V. Vireen, G. Seetharaman, B. Venkataramani","doi":"10.1109/ICED.2008.4786695","DOIUrl":"https://doi.org/10.1109/ICED.2008.4786695","url":null,"abstract":"Wave-pipelining is a technique used in digital systems to achieve maximal rate operation. Higher operating frequencies can be achieved in wave-pipelined digital circuits, by adjusting the clock periods and clock skews so as to latch the output of combinational logic circuits at the stable periods. In the literature, only trial and error and manual procedures are adopted for the choice of the optimum value of the clock frequency and clock skew between input and output registers of the wave-pipelined circuits. The major contribution of this paper is the proposal for automating the above procedure for the ASIC implementation of wave-pipelined circuits. For the purpose of verification, filters using the distributed arithmetic algorithm are implemented. To test the efficacy of the proposed scheme, filters with different taps are implemented by adopting three schemes: wave-pipelining, pipelining and non-pipelining. From the implementation results, it is observed that the wave-pipelined circuits are 21-29% faster compared to non-pipelined circuits. The pipelined circuits are 22-48% faster compared to wave-pipelined circuits but at the cost of about 18-28% increase in area. At normalized frequency, the pipelined circuits are found to be dissipating 3% more power than the wave-pipelined circuits.","PeriodicalId":103889,"journal":{"name":"2008 International Conference on Electronic Design","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126761281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Experiments on data processing algorithms: Energy efficiency of wireless and untethered Field Programmable Gate Array (FPGA)-based embedded systems 数据处理算法的实验:基于无线和非拴现场可编程门阵列(FPGA)的嵌入式系统的能效

2008 International Conference on Electronic Design Pub Date : 2008-12-01 DOI: 10.1504/IJICT.2009.026425

P. Czapski, A. Sluzek

引用次数: 0