{"title":"Electromagnetic field analysis of a broadband antenna built for third-generation mobile and UWB communications considering the effects of dielectric housing","authors":"Y. Akiyama, K. Koshiji, F. Koshiji","doi":"10.1109/ICSJ.2013.6756105","DOIUrl":"https://doi.org/10.1109/ICSJ.2013.6756105","url":null,"abstract":"In recent years, ultra-wideband (UWB) technology has drawn considerable attention as a promising option for the development of ubiquitous networks. In comparison with a conventional narrowband antenna system, the development of an electronic device with a built-in broadband antenna is more difficult because antenna performance must be ensured over the entire UWB frequency band. Previously, we proposed and designed an antenna configuration that serves both the 2 GHz band for third-generation (3G) smartphones and 3.1-10.6 GHz band for UWB technology. In this study, we investigated an antenna configuration with a dielectric housing, which operates over both the 2 GHz and 3.1-10.6 GHz band frequencies. The proposed antenna configuration has excellent VSWR characteristics with values less than 2.0 in both the 3G and UWB frequency bands.","PeriodicalId":101667,"journal":{"name":"2013 3rd IEEE CPMT Symposium Japan","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122942783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Masahiro Terasaki, Sho Kiyosige, W. Ichimura, R. Kobayashi, G. Kubo, H. Otsuka, T. Sudo
{"title":"Power integrity behavior for various packaging environments","authors":"Masahiro Terasaki, Sho Kiyosige, W. Ichimura, R. Kobayashi, G. Kubo, H. Otsuka, T. Sudo","doi":"10.1109/ICSJ.2013.6756112","DOIUrl":"https://doi.org/10.1109/ICSJ.2013.6756112","url":null,"abstract":"Power integrity design has become a critical issue in digital electronic systems, as advanced CMOS LSIs operate at higher clock frequency and at lower supply voltage. Power supply fluctuation excited by core circuits or I/O buffer circuits induces logic instability and electromagnetic radiation. Therefore, total impedance of power distribution network (PDN) must be taking into consideration in the chip-package-board co-design. Especially, anti-resonance peaks in the PDN created by the parallel combination of on-chip capacitance and package inductance induce the unwanted power supply fluctuation, and results in the degradation of signal integrity and electromagnetic interference (EMI). In this paper, effects of critical damping condition for the total PDN impedance on power supply noise has been studied by adding different RC circuit to the intrinsic on-die RC circuit of chip. Three test chips were assumed to be designed on-chip PDN properties. The measurement and analysis of power supply noises for the three test chips showed typical characteristics of oscillatory region and damped regions the critical damping condition against the anti-resonance peak has been proved to be effective to suppress the power supply noise on the chip. Furthermore QFP and BGA are used for a package and the effect of anti-resonance and power supply noise control by the total impedance of a chip package board are verified from the difference in inductance.","PeriodicalId":101667,"journal":{"name":"2013 3rd IEEE CPMT Symposium Japan","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133526293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jinseong Kim, Gyuwan Han, Byoungwoo Cho, Yesul Ahn, Dongjoo Park, Juhoon Yoon, Choon Heung, A. Yoshida
{"title":"Fine pitch PoP introduction","authors":"Jinseong Kim, Gyuwan Han, Byoungwoo Cho, Yesul Ahn, Dongjoo Park, Juhoon Yoon, Choon Heung, A. Yoshida","doi":"10.1109/ICSJ.2013.6756077","DOIUrl":"https://doi.org/10.1109/ICSJ.2013.6756077","url":null,"abstract":"Package-on-package (PoP) has been widely adopted for 3D integration of logic and memory within mobile handsets and other portable multimedia devices. Typical PoP solution is applied to logic processor as bottom package and memory device as top package. TMV® solution is being applied to reduce the warpage and achieve the fine pitch PoP and stable stacking performance. Currently, 0.4mm MIF(Memory Interface Pitch) is the minimum pitch under production and more fine MIF pitch is being requested because more functions are being integrated on chip then chip size becomes larger even wafer node is going narrower. To sustain the similar package size with larger chip size, fine pitch PoP is required. In this paper, 0.3 and 0.27mm MIF pitch PoP will be studied as a solution for fine pitch PoP and as a interface material between Top and Bottom package, solder ball and Cu post will be evaluated.","PeriodicalId":101667,"journal":{"name":"2013 3rd IEEE CPMT Symposium Japan","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132051305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Sasaki, Y. Okabe, M. Ueno, T. Sakamoto, S. Toyoda, J. Kobayashi, S. Yagi, K. Naganuma
{"title":"High-speed KTN optical beam deflector for swept-source optical coherence tomography","authors":"Y. Sasaki, Y. Okabe, M. Ueno, T. Sakamoto, S. Toyoda, J. Kobayashi, S. Yagi, K. Naganuma","doi":"10.1109/ICSJ.2013.6756100","DOIUrl":"https://doi.org/10.1109/ICSJ.2013.6756100","url":null,"abstract":"We have developed an electro-optic (EO) optical beam deflector using KTa1-xNbxO3 (KTN) crystal. The combination of the huge second order EO (Kerr) effect of KTN crystal and control of the electron injection into the crystal makes the deflection angle appreciable. We describe the operation principle for this fast and large angle deflection. We also describe the packaging of the KTN deflector and beam shaping lenses at the high-frequency deflection. We built swept light sources equipped with a KTN deflector for optical coherence tomography (OCT). With OCT, an imaging technique using laser interferometry, it is possible to obtain depth-resolved information about biological tissue with micrometer-scale spatial resolution. A 200-kHz scan rate was obtained with a 20-mW average output power at a scan range exceeding 100 nm. The coherence length measured by using the relative signal decay from a different path delay is 7 mm. We obtained OCT images of biological tissue using our swept light source OCT system.","PeriodicalId":101667,"journal":{"name":"2013 3rd IEEE CPMT Symposium Japan","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115559992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Aozasa, Y. Kurata, Y. Hashizume, M. Itoh, H. Fukuyama
{"title":"Thermal via technology for silica-based planar lightwave circuit","authors":"S. Aozasa, Y. Kurata, Y. Hashizume, M. Itoh, H. Fukuyama","doi":"10.1109/ICSJ.2013.6756092","DOIUrl":"https://doi.org/10.1109/ICSJ.2013.6756092","url":null,"abstract":"We propose the first thermal via technology for a silica-based planar lightwave circuit (PLC) to enable us to stack electronic components such as transimpedance amplifiers (TIAs) on a PLC. This is possible because the effective heat dissipation of the via can prevent the performance degradation of the TIA. The temperature increase of the TIAs was suppressed to only 8.7°C by the thermal vias, while it was 15.7°C without them. Silica-based PLCs with thermal vias will be a key technology for compact high performance PLC devices.","PeriodicalId":101667,"journal":{"name":"2013 3rd IEEE CPMT Symposium Japan","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130746037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Takanori Shimizu, N. Hatori, M. Ishizaka, Y. Urino, Tsuyoshi Yamamoto, Takahiro Nakamura, M. Okano, M. Mori, Y. Arakawa
{"title":"Hybrid integration technology of laser source with laser diode arrays on silicon optical waveguide platform by flip-chip bonding for silicon photonics","authors":"Takanori Shimizu, N. Hatori, M. Ishizaka, Y. Urino, Tsuyoshi Yamamoto, Takahiro Nakamura, M. Okano, M. Mori, Y. Arakawa","doi":"10.1109/ICSJ.2013.6756091","DOIUrl":"https://doi.org/10.1109/ICSJ.2013.6756091","url":null,"abstract":"Hybrid integration technology of a laser source on a silicon optical waveguide platform by flip-chip bonding for silicon photonics has been developed. Several types of integrated laser sources were demonstrated, including multi-channel, high-density and high temperature operation.","PeriodicalId":101667,"journal":{"name":"2013 3rd IEEE CPMT Symposium Japan","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131226097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kumpei Yamada, D. Fujimoto, Tetsuro Iwakura, H. Murai, Youichi Kaneko, Hiroshi Simizu
{"title":"Airfoil: A new fine line fabrication technology on glass-cloth prepreg without insulating films for PKG substrate","authors":"Kumpei Yamada, D. Fujimoto, Tetsuro Iwakura, H. Murai, Youichi Kaneko, Hiroshi Simizu","doi":"10.1109/ICSJ.2013.6756078","DOIUrl":"https://doi.org/10.1109/ICSJ.2013.6756078","url":null,"abstract":"As electronic parts increase its performance and miniaturize the size, package substrates are demanded to be thinner as well as higher in density. Thin packages such as Chip Scale Package (CSP) require high elastic modulus and low coefficient of thermal expansion with high density wiring to reduce warpage. To enable high density wiring, while maintaining crucial properties and minimal warpage, various fine line fabrications applied to glass-cloth prepreg have been investigated. The wiring processes with glass-cloth prepreg have made much progress from the subtractive method to SAP (Semi-Additive Process with primer for glass-cloth prepreg) and MSAP (modified SAP with ultra-thin copper). These have been achieved by decreasing the thickness of the to-be-etched copper layer. In the conventional SAP, the roughened surface of the primer is formed by imprinting the low profile copper (Ra = 0.3-0.5 μm) instead of the chemical etching of insulation film [1]. However, the flatness of the surface of Ra;0.3-0.5 μm makes the wiring under 30 μm pitch difficult. Therefore, we developed the new primer “Airfoil”, that can provide the excellent adhesive property with plated copper via chemical interaction. Airfoil has functional groups interacting with plated copper which provide the excellent peel strength despite of smooth surface (Ra<;0.1 μm). In addition, the high peel strength of Airfoil can be maintained for various types of prepregs by the diffusion controlled adhesive process. By applying Airfoil with glass-cloth prepreg, the wiring of 10 μm pitch was successfully fabricated by the SAP. Since Airfoil is very thin, it does not influence the prime properties of glass-cloth prepreg (e.g. elastic modulus, coefficient of thermal expansion, dielectric properties). Consequently, the package substrates of Airfoil with prepreg show the low coefficient of thermal expansion and high elastic modulus with 10 μm pitch wiring.","PeriodicalId":101667,"journal":{"name":"2013 3rd IEEE CPMT Symposium Japan","volume":"156 52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130459530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Randeep Singh, M. Mochizuki, Mohammed Ahamed Shahed, Yuji Saito, Ahmed Jalilvand, M. Matsuda, Yoji Kawahara, K. Goto
{"title":"Low profile cooling solutions for advanced packaging based on ultra-thin heat pipe and piezo fan","authors":"Randeep Singh, M. Mochizuki, Mohammed Ahamed Shahed, Yuji Saito, Ahmed Jalilvand, M. Matsuda, Yoji Kawahara, K. Goto","doi":"10.1109/ICSJ.2013.6756110","DOIUrl":"https://doi.org/10.1109/ICSJ.2013.6756110","url":null,"abstract":"In this paper, heat pipes and piezo fan, in combination as well as individually, has been proposed to provide very thin thermal solutions for high density electronic packaging. Ultra-thin heat pipes with thickness in range of 0.6 to 2 mm have been developed to transfer maximum heat load of 0.8 to 68W respectively. These heat pipes have been fabricated from copper-water combination with center fiber copper wick. Different type of piezo fans (low frequency flapping type, high flow rate type and high velocity impingement type) with small thickness ~ 0.8 to 2 mm, low power consumption and high reliability has been proposed and characterized. These fans can provide direct cooling system or can be combined with thin heat pipe to provide remote heat exchanger. Using these thin advanced thermal technologies, cooling modules with thermal capability of 3 to 10 W and maximum thickness of 0.7 to 6 mm respectively has been designed and characterized. In summary, thermal technologies and cooling modules developed in this research work will provide energy efficient and thin thermal management solutions for space conservative high density electronics.","PeriodicalId":101667,"journal":{"name":"2013 3rd IEEE CPMT Symposium Japan","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128170890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Hashimoto, Y. Akiyama, C. Ueda, Tsuneo Ito, K. Otsuka
{"title":"Power/ground wiring for high speed driver: Evaluating method by comparison with actual and simulation schemes","authors":"K. Hashimoto, Y. Akiyama, C. Ueda, Tsuneo Ito, K. Otsuka","doi":"10.1109/ICSJ.2013.6756113","DOIUrl":"https://doi.org/10.1109/ICSJ.2013.6756113","url":null,"abstract":"In our previous studies [1], [2], good power supply wirings on a chip have provided excellent high-speed switching and tinny power swing fluctuation. In this study, we again confirmed this by higher precision re-measurements correlated with simulations. If the power integrity (PI) would be better on the circuit, the circuit would be expected that the CMOS driver makes it sure to take higher-speed switching. Such kind of scheme had not been tried previously, because the power line performance expression by SPICE tool had to be difficult to coincident with actual power line. We planed to build the power supply circuit model by SPICE tool reflected faithfully with the test coupon. As the simulation model from the transmission line for the power line is coincided with actual physical structure, we can make the concept how to design and produce circuits from the variation of simulation results. Then we can get the key design rule for over Gbps region on a input/output (I/O) interface circuit system.","PeriodicalId":101667,"journal":{"name":"2013 3rd IEEE CPMT Symposium Japan","volume":"241 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121167253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hiroyoshi Kawasaki, T. Hattori, Takahiro Roppongi, Daisuke Soma, Yuji Kawamata
{"title":"Cu balls and Cu-core balls for 3D packaging","authors":"Hiroyoshi Kawasaki, T. Hattori, Takahiro Roppongi, Daisuke Soma, Yuji Kawamata","doi":"10.1109/ICSJ.2013.6756080","DOIUrl":"https://doi.org/10.1109/ICSJ.2013.6756080","url":null,"abstract":"The use of Cu balls and Cu-core balls is focused on 3D packaging technology to maintain a stable standoff height. However, these materials show unique soldering behaviors that are different from solder balls. In this paper, we examine how to utilize them.","PeriodicalId":101667,"journal":{"name":"2013 3rd IEEE CPMT Symposium Japan","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121819903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}