Journal of Microcomputer Applications最新文献_第10页

Journal of Microcomputer Applications Pub Date : 1994-04-01 DOI: 10.1006/jmca.1994.1008

Le Gruenwald, Jing Huang

引用次数: 0

Journal of Microcomputer Applications Pub Date : 1994-04-01 DOI: 10.1006/JMCA.1994.1008

L. Gruenwald, Jing Huang

引用次数: 0

Efficient barrier synchronization techniques and their applications in large-scale shared memory multiprocessors 高效屏障同步技术及其在大规模共享内存多处理器中的应用

Journal of Microcomputer Applications Pub Date : 1994-04-01 DOI: 10.1006/JMCA.1994.1012

K. Ghose, D. Cheng

{"title":"Efficient barrier synchronization techniques and their applications in large-scale shared memory multiprocessors","authors":"K. Ghose, D. Cheng","doi":"10.1006/JMCA.1994.1012","DOIUrl":"https://doi.org/10.1006/JMCA.1994.1012","url":null,"abstract":"Abstract Shared memory multiprocessors offer a relatively simple programming model and are suitable for a wide variety of parallel applications. Unfortunately, shared memory multiprocessors are not as scalable as distributed memory multiprocessors owing to memory and switch contentions that can result in the formation of hot spots. Spinning on synchronization variables appears to be the main culprit behind the formation of hot spots, affecting system scalability adversely. The purpose of this paper is to address the issue of performing barrier synchronization efficiently in large-scale shared memory multiprocessors. We propose a very simple design for a hardware barrier synchronizer that has the characteristics of what one would call an ideal barrier synchronizer. In particular, the proposed barrier synchronizer allows fast barrier synchronization without injecting spin traffic to create hot spots and can be reused as soon as it has completed a barrier synchronization. We also show that by augmenting this barrier synchronizer with a few gates, it can be used to perform dynamic barrier synchronization, where neither the number, nor the exact identity of processors participating in the barrier is known a priori. We will also show that a low-latency barrier synchronizer can be used not only for high-speed barrier synchronization but also, very profitably, for implementing software combining (allowing distributed hot spot accessing), for data and producer-consumer type synchronization and for the implementation of a variety of other useful applications. A high-speed barrier synchronizer can also be used to implement highly concurrent data structures and will also allow a MIMD (Multiple Instruction streams, Multiple Data streams) system to be effectively operated in a SIMD (Single Instruction stream, Multiple Data streams)-style mode, giving rise to a number of potential advantages. We use simulations to confirm that our proposed synchronizers and their applications outperform the existing barrier synchronization schemes.","PeriodicalId":100806,"journal":{"name":"Journal of Microcomputer Applications","volume":"9 3","pages":"197-221"},"PeriodicalIF":0.0,"publicationDate":"1994-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91506503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Optimal cube-connected cube multicomputers 最佳立方体连接立方体多计算机

Journal of Microcomputer Applications Pub Date : 1994-04-01 DOI: 10.1006/jmca.1994.1009

Jie Wu, Xian-He Sun

{"title":"Optimal cube-connected cube multicomputers","authors":"Jie Wu, Xian-He Sun","doi":"10.1006/jmca.1994.1009","DOIUrl":"https://doi.org/10.1006/jmca.1994.1009","url":null,"abstract":"<div>Many CFD (computational fluid dynamics) and other scientific applications can be partitioned into subproblems. However, in general, the partitioned subproblems are very large. They demand high-performance computing power themselves, and their solutions have to be combined at each time step. In this paper, the cube-connect cube (CCCube) architecture is studied. The CCCube architecture is an extended hypercube structure with each node represented as a cube. It requires fewer physical links between nodes than the hypercube, and provides the same communication support as the hypercube does on many applications. The reduced physical links can be used to enhance the bandwidth of the remanding links and, therefore, enhance the overall performance. The concept and the method to obtain optimal CCCubes, which are the CCCubes with a minimum number of links under a given total number of nodes, are proposed. The superiority of optimal CCCubes over standard hypercubes has also been shown in terms of the link usage in the embedding of a binomial tree. A useful computation structure based on a semi-binomial tree for divide-and-conquer type of parallel algorithms has been identified. We have shown that this structure can be implemented in optimal CCCubes without performance degradation compared with regular hypercubes. The result presented in this paper should provide a useful approach to design of scientific parallel computers.</div>","PeriodicalId":100806,"journal":{"name":"Journal of Microcomputer Applications","volume":"17 2","pages":"Pages 135-146"},"PeriodicalIF":0.0,"publicationDate":"1994-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1006/jmca.1994.1009","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71734056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Multiprocessing in multiprotocol routers 多协议路由器中的多处理

Journal of Microcomputer Applications Pub Date : 1994-04-01 DOI: 10.1006/JMCA.1994.1007

D. Serpanos

引用次数: 1

Special Issue on Parallel and Multiprocessor Systems 并行和多处理器系统特刊

Journal of Microcomputer Applications Pub Date : 1994-04-01 DOI: 10.1006/jmca.1994.1006

Nikolaos G. Bourbakis

引用次数: 0

A dynamically scheduled parallel DSP architecture for stream flow programming 一个动态调度并行DSP体系结构的流流编程

Journal of Microcomputer Applications Pub Date : 1994-04-01 DOI: 10.1006/jmca.1994.1011

Guoning Liao, Guang R. Gao, Vinod K. Agarwal

{"title":"A dynamically scheduled parallel DSP architecture for stream flow programming","authors":"Guoning Liao, Guang R. Gao, Vinod K. Agarwal","doi":"10.1006/jmca.1994.1011","DOIUrl":"https://doi.org/10.1006/jmca.1994.1011","url":null,"abstract":"<div>This paper presents a dynamically scheduled parallel DSP architecture for general purpose DSP computations. The architecture consists of multiple DSP processors and of one or more scheduling units. DSP applications are first captured by stream flow graphs, and then stream flow graphs are statically mapped onto a parallel architecture. The ordering and starting time of DSP tasks are determined by the scheduling unit(s) using a dynamic scheduling algorithm.The main contributions of this paper are summarized as follows:• A scalable parallel DSP architecture: The parallel DSP architecture proposed in this paper is scalable to meet signal processing requirements. For parallel DSP architectures with large configurations, the scheduling unit may become a performance bottleneck. A distributed scheduling mechanism is proposed to address this problem.• A mapping algorithm: An algorithm is proposed to systematically map a stream flow graph onto a parallel DSP architecture.• A dynamic scheduling algorithm: We propose a dynamic scheduling algorithm that will only schedule a node for execution when both input data and output storage space are available. Such scheduling algorithm will allow buffer sizes to be determined at compile time.• A simulation study: Our simulation study reveals the relationships among the grain-size, the processor utilization, and the scheduling capability. We believe these relationships have significant impact on parallel computer architecture design involving dynamic scheduling.</div>","PeriodicalId":100806,"journal":{"name":"Journal of Microcomputer Applications","volume":"17 2","pages":"Pages 171-196"},"PeriodicalIF":0.0,"publicationDate":"1994-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1006/jmca.1994.1011","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71734058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Special Issue on Parallel and Multiprocessor Systems 并行和多处理器系统特刊

Journal of Microcomputer Applications Pub Date : 1994-04-01 DOI: 10.1006/jmca.1994.1006

N. Bourbakis

引用次数: 0

A dynamically scheduled parallel DSP architecture for stream flow programming 一个动态调度并行DSP体系结构的流流编程

Journal of Microcomputer Applications Pub Date : 1994-04-01 DOI: 10.1006/JMCA.1994.1011

Guoning Liao, G. Gao, V. Agarwal

{"title":"A dynamically scheduled parallel DSP architecture for stream flow programming","authors":"Guoning Liao, G. Gao, V. Agarwal","doi":"10.1006/JMCA.1994.1011","DOIUrl":"https://doi.org/10.1006/JMCA.1994.1011","url":null,"abstract":"Abstract This paper presents a dynamically scheduled parallel DSP architecture for general purpose DSP computations. The architecture consists of multiple DSP processors and of one or more scheduling units. DSP applications are first captured by stream flow graphs, and then stream flow graphs are statically mapped onto a parallel architecture. The ordering and starting time of DSP tasks are determined by the scheduling unit(s) using a dynamic scheduling algorithm. The main contributions of this paper are summarized as follows: • A scalable parallel DSP architecture : The parallel DSP architecture proposed in this paper is scalable to meet signal processing requirements. For parallel DSP architectures with large configurations, the scheduling unit may become a performance bottleneck. A distributed scheduling mechanism is proposed to address this problem. • A mapping algorithm : An algorithm is proposed to systematically map a stream flow graph onto a parallel DSP architecture. • A dynamic scheduling algorithm : We propose a dynamic scheduling algorithm that will only schedule a node for execution when both input data and output storage space are available. Such scheduling algorithm will allow buffer sizes to be determined at compile time. • A simulation study : Our simulation study reveals the relationships among the grain-size, the processor utilization, and the scheduling capability. We believe these relationships have significant impact on parallel computer architecture design involving dynamic scheduling.","PeriodicalId":100806,"journal":{"name":"Journal of Microcomputer Applications","volume":"25 1","pages":"171-196"},"PeriodicalIF":0.0,"publicationDate":"1994-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88452131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A parallel hardware approach to implement network protocols 实现网络协议的并行硬件方法

Journal of Microcomputer Applications Pub Date : 1994-04-01 DOI: 10.1006/jmca.1994.1010

V. Catania, S. Cavalieri, A. Puliafito, L. Vita

引用次数: 0