A parallel hardware approach to implement network protocols

V. Catania, S. Cavalieri, A. Puliafito, L. Vita
{"title":"A parallel hardware approach to implement network protocols","authors":"V. Catania,&nbsp;S. Cavalieri,&nbsp;A. Puliafito,&nbsp;L. Vita","doi":"10.1006/jmca.1994.1010","DOIUrl":null,"url":null,"abstract":"<div><p>The dramatic increase in the operating bandwidth of current communication networks requires a very high processing speed for communications protocols to offer users real broadband services.</p><p>Although there are different causes determining slowness in protocol processing, some implementation approaches for communication protocols seem to be the most limiting factor. This paper proposes a parallel architecture, based on VLSI components, to implement the OSI stack system in HSLANs and MANs. The proposed architecture is coupled with a model based on Petri nets which can characterize the implementation of each level according to the necessary requirements. We show that a hard protocol, as the data link layer, implemented according to the proposed architecture can effectively work at a data rate which is adequate for current networks.</p></div>","PeriodicalId":100806,"journal":{"name":"Journal of Microcomputer Applications","volume":"17 2","pages":"Pages 147-170"},"PeriodicalIF":0.0000,"publicationDate":"1994-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1006/jmca.1994.1010","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Microcomputer Applications","FirstCategoryId":"1085","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0745713884710104","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

Abstract

The dramatic increase in the operating bandwidth of current communication networks requires a very high processing speed for communications protocols to offer users real broadband services.

Although there are different causes determining slowness in protocol processing, some implementation approaches for communication protocols seem to be the most limiting factor. This paper proposes a parallel architecture, based on VLSI components, to implement the OSI stack system in HSLANs and MANs. The proposed architecture is coupled with a model based on Petri nets which can characterize the implementation of each level according to the necessary requirements. We show that a hard protocol, as the data link layer, implemented according to the proposed architecture can effectively work at a data rate which is adequate for current networks.

实现网络协议的并行硬件方法
当前通信网络的操作带宽的急剧增加要求通信协议具有非常高的处理速度,以向用户提供真正的宽带服务。尽管有不同的原因决定了协议处理的缓慢,但通信协议的一些实现方法似乎是最受限制的因素。本文提出了一种基于超大规模集成电路组件的并行体系结构,以实现HSLAN和MANs中的OSI堆栈系统。所提出的体系结构与一个基于Petri网的模型相结合,该模型可以根据必要的需求来描述每个级别的实现。我们表明,根据所提出的架构实现的作为数据链路层的硬协议可以有效地以适合当前网络的数据速率工作。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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