Multiprocessing in multiprotocol routers

Abstract High-speed networks place strict requirements on the architecture of communication subsystems. One of the most significant problems in conventional subsystems is provision of high-speed protocol processing. The protocol processing problem is especially significant in the environment of multiprotocol routers where several routing protocols are supported. A multiprocessor architecture for high-speed processing in multiprotocol environments is presented and analyzed. It is shown that exploitation of vertical and horizontal parallelism in protocol stacks combined with parallelism in memory accesses and packet memory management significantly increases system performance. The presented architecture, used in realistic environments, meets the throughput requirements of high-speed network links offering throughput up to 100 Mbps.