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A parallel architecture for performing mail sorting in real time 用于实时执行邮件排序的并行体系结构
Journal of Microcomputer Applications Pub Date : 1994-07-01 DOI: 10.1006/jmca.1994.1017
David L. Andrews, Arthur R. Hennessey
{"title":"A parallel architecture for performing mail sorting in real time","authors":"David L. Andrews,&nbsp;Arthur R. Hennessey","doi":"10.1006/jmca.1994.1017","DOIUrl":"https://doi.org/10.1006/jmca.1994.1017","url":null,"abstract":"<div><p>This paper describes a special-purpose embedded multiprocessor architecture developed for performing real-time multi-line optical character recognition (MLOCR). MLOCR is a computationally intensive real-time application involving pattern recognition, character image extraction, gray-scale thresholding, rotation and scaling of individual characters, and character identification. The computational complexity of the MLOCR application dictated the development of custom hardware in a parallel processing environment in order to meet the real-time system requirements. The overall system organization is described, along with the functional partitioning of algorithms onto processors, development of specific custom hardware to implement the algorithms in real time, interprocess communications, and system control.</p></div>","PeriodicalId":100806,"journal":{"name":"Journal of Microcomputer Applications","volume":"17 3","pages":"Pages 273-286"},"PeriodicalIF":0.0,"publicationDate":"1994-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1006/jmca.1994.1017","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71740251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
SELAC—statistical error location and correction for secondary memory storage 辅助存储器存储的统计错误定位和校正
Journal of Microcomputer Applications Pub Date : 1994-07-01 DOI: 10.1006/JMCA.1994.1016
R. Rowell, V. Nair
{"title":"SELAC—statistical error location and correction for secondary memory storage","authors":"R. Rowell, V. Nair","doi":"10.1006/JMCA.1994.1016","DOIUrl":"https://doi.org/10.1006/JMCA.1994.1016","url":null,"abstract":"Abstract In this paper a statistical approach to error location and correction for data stored in secondary memories is developed. The approach is based on the observation that the data records in secondary storage have some inherent redundancy of information. This redundancy cannot precisely be predicted as in the case of typical error correction scheme's artificial redundancy. However, the redundancy can be exploited to provide error correction with some degree of confidence. We use simple and weighted checksum schemes for error detection and present algorithms for single and multiple error correction using statistical error location and correction (SELAC). An implementation of SELAC will be described with an elaborate study of its error-correction capabilities. A conspicuous aspect of SELAC is that it will not cost any processor time and storage overhead until after an error is encountered, unlike the classical schemes using single error correcting-double error detecting (SEC-DED) and double error correcting-triple error detecting (DEC-TED) codes.","PeriodicalId":100806,"journal":{"name":"Journal of Microcomputer Applications","volume":"17 1","pages":"255-271"},"PeriodicalIF":0.0,"publicationDate":"1994-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79666210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A parallel architecture for performing mail sorting in real time 用于实时执行邮件排序的并行体系结构
Journal of Microcomputer Applications Pub Date : 1994-07-01 DOI: 10.1006/JMCA.1994.1017
D. Andrews, A. Hennessey
{"title":"A parallel architecture for performing mail sorting in real time","authors":"D. Andrews, A. Hennessey","doi":"10.1006/JMCA.1994.1017","DOIUrl":"https://doi.org/10.1006/JMCA.1994.1017","url":null,"abstract":"Abstract This paper describes a special-purpose embedded multiprocessor architecture developed for performing real-time multi-line optical character recognition (MLOCR). MLOCR is a computationally intensive real-time application involving pattern recognition, character image extraction, gray-scale thresholding, rotation and scaling of individual characters, and character identification. The computational complexity of the MLOCR application dictated the development of custom hardware in a parallel processing environment in order to meet the real-time system requirements. The overall system organization is described, along with the functional partitioning of algorithms onto processors, development of specific custom hardware to implement the algorithms in real time, interprocess communications, and system control.","PeriodicalId":100806,"journal":{"name":"Journal of Microcomputer Applications","volume":"47 2 1","pages":"273-286"},"PeriodicalIF":0.0,"publicationDate":"1994-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77309471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Synthesis of automata from elements with given constraints on their complexity 具有给定复杂性约束的元素的自动机合成
Journal of Microcomputer Applications Pub Date : 1994-07-01 DOI: 10.1006/JMCA.1994.1014
S. Baranov, L. Bregman
{"title":"Synthesis of automata from elements with given constraints on their complexity","authors":"S. Baranov, L. Bregman","doi":"10.1006/JMCA.1994.1014","DOIUrl":"https://doi.org/10.1006/JMCA.1994.1014","url":null,"abstract":"Abstract Techniques for logic synthesis of control units from elements with given constraints on their complexity are presented. Programmable logic arrays (PLA) with restrictions on the number of inputs, outputs and terms are used as an example of such elements. Two synthesis methods are suggested: terms distribution and distribution of pairs (term, function), and two algorithms, precise and approximate, are described. The results of computational experiments with these algorithms are discussed.","PeriodicalId":100806,"journal":{"name":"Journal of Microcomputer Applications","volume":"5 1 1","pages":"227-237"},"PeriodicalIF":0.0,"publicationDate":"1994-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76069154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
DOP—a simple processor for custom computing machines 用于定制计算机的简单处理器
Journal of Microcomputer Applications Pub Date : 1994-07-01 DOI: 10.1006/jmca.1994.1015
Jiřı́ Daněček, František Drápal, Alois Pluháček, Zoran Salčič, Michal Servı́t
{"title":"DOP—a simple processor for custom computing machines","authors":"Jiřı́ Daněček,&nbsp;František Drápal,&nbsp;Alois Pluháček,&nbsp;Zoran Salčič,&nbsp;Michal Servı́t","doi":"10.1006/jmca.1994.1015","DOIUrl":"https://doi.org/10.1006/jmca.1994.1015","url":null,"abstract":"<div><p>A general-purpose processor cell, called DOP, is presented. The DOP architecture is designed to support efficiently high-level programming languages (HLLs) such as C or Pascal, but still be simple enough to be implemented on one field programmable gate array (FPGA). Special attention is paid to the analysis of HLL requirements on processors. The DOP is designed to be used as a building block (cell) in a FPGA library. Its simplicity allows other microcomputer functional units to be implemented on the same FPGA. The DOP serves as a core for simple solutions using currently available technology.</p></div>","PeriodicalId":100806,"journal":{"name":"Journal of Microcomputer Applications","volume":"17 3","pages":"Pages 239-253"},"PeriodicalIF":0.0,"publicationDate":"1994-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1006/jmca.1994.1015","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71740299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Microcomputer control of electric drives 微电脑控制的电力驱动
Journal of Microcomputer Applications Pub Date : 1994-07-01 DOI: 10.1006/jmca.1994.1019
Jiřı́ Javůrek
{"title":"Microcomputer control of electric drives","authors":"Jiřı́ Javůrek","doi":"10.1006/jmca.1994.1019","DOIUrl":"https://doi.org/10.1006/jmca.1994.1019","url":null,"abstract":"<div><p>The microcontrollers of the INTEL '196 family are used for covering drive control and regulation, which are essential functions supporting research, development and service purposes. The converter controller has been manipulated by a PC host computer to order all requests to control and regulation. The field-oriented method and the direct torque control method have been used in an experiment drive in the laboratory of the Department of Electrical Machines, Apparatus and Drives. The basic properties and possibilities of both methods were experimentally verified. The results obtained are used for educational purposes and for problem-solving by Czech industry.</p></div>","PeriodicalId":100806,"journal":{"name":"Journal of Microcomputer Applications","volume":"17 3","pages":"Pages 299-309"},"PeriodicalIF":0.0,"publicationDate":"1994-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1006/jmca.1994.1019","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71740253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Synthesis of automata from elements with given constraints on their complexity 具有给定复杂性约束的元素的自动机合成
Journal of Microcomputer Applications Pub Date : 1994-07-01 DOI: 10.1006/jmca.1994.1014
S. Baranov, L. Bregman
{"title":"Synthesis of automata from elements with given constraints on their complexity","authors":"S. Baranov,&nbsp;L. Bregman","doi":"10.1006/jmca.1994.1014","DOIUrl":"https://doi.org/10.1006/jmca.1994.1014","url":null,"abstract":"<div><p>Techniques for logic synthesis of control units from elements with given constraints on their complexity are presented. Programmable logic arrays (PLA) with restrictions on the number of inputs, outputs and terms are used as an example of such elements. Two synthesis methods are suggested: terms distribution and distribution of pairs (term, function), and two algorithms, precise and approximate, are described. The results of computational experiments with these algorithms are discussed.</p></div>","PeriodicalId":100806,"journal":{"name":"Journal of Microcomputer Applications","volume":"17 3","pages":"Pages 227-237"},"PeriodicalIF":0.0,"publicationDate":"1994-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1006/jmca.1994.1014","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"71740300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Special Issue on Real-time Applications, Design Techniques, Diagnostics and Reliability 实时应用、设计技术、诊断和可靠性特刊
Journal of Microcomputer Applications Pub Date : 1994-07-01 DOI: 10.1006/jmca.1994.1013
Z. Blazek
{"title":"Special Issue on Real-time Applications, Design Techniques, Diagnostics and Reliability","authors":"Z. Blazek","doi":"10.1006/jmca.1994.1013","DOIUrl":"https://doi.org/10.1006/jmca.1994.1013","url":null,"abstract":"","PeriodicalId":100806,"journal":{"name":"Journal of Microcomputer Applications","volume":"20 1","pages":"225"},"PeriodicalIF":0.0,"publicationDate":"1994-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86273345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low-cost microcontroller driven ECG 低成本单片机驱动心电
Journal of Microcomputer Applications Pub Date : 1994-07-01 DOI: 10.1006/JMCA.1994.1020
Z. Blazek, J. Janecek
{"title":"Low-cost microcontroller driven ECG","authors":"Z. Blazek, J. Janecek","doi":"10.1006/JMCA.1994.1020","DOIUrl":"https://doi.org/10.1006/JMCA.1994.1020","url":null,"abstract":"Abstract This paper describes the design of a simple, low-cost device for surgeries, ambulances, etc. A 12-lead ECG is discussed. We shall describe the basic version and its hardware and software.","PeriodicalId":100806,"journal":{"name":"Journal of Microcomputer Applications","volume":"1 1","pages":"311-315"},"PeriodicalIF":0.0,"publicationDate":"1994-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84074103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimal cube-connected cube multicomputers 最佳立方体连接立方体多计算机
Journal of Microcomputer Applications Pub Date : 1994-04-01 DOI: 10.1006/JMCA.1994.1009
Jie Wu, Xian-He Sun
{"title":"Optimal cube-connected cube multicomputers","authors":"Jie Wu, Xian-He Sun","doi":"10.1006/JMCA.1994.1009","DOIUrl":"https://doi.org/10.1006/JMCA.1994.1009","url":null,"abstract":"Abstract Many CFD (computational fluid dynamics) and other scientific applications can be partitioned into subproblems. However, in general, the partitioned subproblems are very large. They demand high-performance computing power themselves, and their solutions have to be combined at each time step. In this paper, the cube-connect cube (CCCube) architecture is studied. The CCCube architecture is an extended hypercube structure with each node represented as a cube. It requires fewer physical links between nodes than the hypercube, and provides the same communication support as the hypercube does on many applications. The reduced physical links can be used to enhance the bandwidth of the remanding links and, therefore, enhance the overall performance. The concept and the method to obtain optimal CCCubes, which are the CCCubes with a minimum number of links under a given total number of nodes, are proposed. The superiority of optimal CCCubes over standard hypercubes has also been shown in terms of the link usage in the embedding of a binomial tree. A useful computation structure based on a semi-binomial tree for divide-and-conquer type of parallel algorithms has been identified. We have shown that this structure can be implemented in optimal CCCubes without performance degradation compared with regular hypercubes. The result presented in this paper should provide a useful approach to design of scientific parallel computers.","PeriodicalId":100806,"journal":{"name":"Journal of Microcomputer Applications","volume":"46 1","pages":"135-146"},"PeriodicalIF":0.0,"publicationDate":"1994-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85982069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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