{"title":"Implementation of Low-Powered Flexible OTFT Compact Model for Digital Logic Circuits Simulation","authors":"Mukuljeet Singh Mehrolia;Simran Grover;Ankit Verma;Navneet Gandhi;Jogendra Singh Rana;Md. Hasnain Ansari;Rekib Uddin Ahmed;Sumit Gaur;Abhishek Kumar Singh","doi":"10.1109/JFLEX.2026.3707166","DOIUrl":"https://doi.org/10.1109/JFLEX.2026.3707166","url":null,"abstract":"This article presents a compact model of the fabricated low-voltage, flexible thin-film transistor (TFT) with a PBTTT-C14-based active semiconductive layer and a strontium zirconate (SrZrO<sub>x</sub>)/polymethyl methacrylate (PMMA) blend-based high-k dielectric layer for the half adder/subtractor and cross-coupled inverter circuit implementation. The fabricated organic TFT (OTFT) was operated at a low voltage of 1 V and was compactly modeled using the Silvaco–Techmodeler tool, which gives good agreement between device modeling and fabricated results, confirming its high accuracy, as a negligible amount of error is observed, which is less than 1% (0.37% and 0.74%). The modeling of the fabricated OTFT has utilized fabricated parameters: a 50-<inline-formula> <tex-math>$mu $ </tex-math></inline-formula>m channel length, 18.03 mm interdigitated length, active and dielectric layer thicknesses of 30 and 60 nm, respectively, and the device shows a 0.27 V threshold voltage and a 200 mV/decade subthreshold swing, 0.06 cm<sup>2</sup>/V<inline-formula> <tex-math>${}^{mathrm {-s}}$ </tex-math></inline-formula> mobility, and an <inline-formula> <tex-math>$I_{mathrm {on}}$ </tex-math></inline-formula>/<inline-formula> <tex-math>$I_{mathrm {off}}$ </tex-math></inline-formula> ratio of <inline-formula> <tex-math>$10^{mathrm {5,}}$ </tex-math></inline-formula> accurately matched with experimental results. This compact-modeled PBTTT-C14 OTFT device is further used for the implementation of a cross-coupled inverter, half subtractor, and half adder circuits using the Silvaco–Gateway tool, and transient analysis is also performed to check its proper functionality. The truth tables for all these circuits are also verified for digital logic operations. The output expressions of sum (AB<inline-formula> <tex-math>${}^{prime } +$ </tex-math></inline-formula>A<inline-formula> <tex-math>${}^{prime }$ </tex-math></inline-formula>B), carry (AB), difference (AB<inline-formula> <tex-math>${}^{prime } +$ </tex-math></inline-formula>A<inline-formula> <tex-math>${}^{prime }$ </tex-math></inline-formula>B), and borrow (A<inline-formula> <tex-math>${}^{prime }$ </tex-math></inline-formula>B) for half adder and half subtractor circuits are successfully verified for all possible 2-bit input combinations (00, 01, 10, 11). The output results show satisfactory results with good logic swing. This proposed flexible PBTTT-C 14-based compact modeled OTFT can be used in the near future for the realization of complex memory and ALU circuits.","PeriodicalId":100623,"journal":{"name":"IEEE Journal on Flexible Electronics","volume":"5 9","pages":"340-345"},"PeriodicalIF":0.0,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148903177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Anil Pandya;Devang Anadkat;Shreya Dungani;Ajay D. Thakur;Anup V. Sanchela
{"title":"Development of Hand-Printed Flexible Graphene/Graphite Thermocouple Sensors on Paper","authors":"Anil Pandya;Devang Anadkat;Shreya Dungani;Ajay D. Thakur;Anup V. Sanchela","doi":"10.1109/JFLEX.2026.3707168","DOIUrl":"https://doi.org/10.1109/JFLEX.2026.3707168","url":null,"abstract":"Accurate, sustainable, and low-cost temperature sensing is vital for the advancement of modern technologies such as wearable, flexible, and disposable electronics. However, the limited thermoelectric performance of polymer-based materials and the rigidity of conventional inorganic thermocouples hinder the development of a flexible thermocouple with high sensitivity and mechanical durability. In this work, we present a fully carbon-based thermoelectric sensor fabricated using few-layer graphene (FLG) traces, and pencil-grade (HB and 6B) graphite paints on standard Xerox paper. Despite having lower graphite content in HB-grade compared to 6B-grade, the HB-grade graphite paint exhibits higher conductivity (<inline-formula> <tex-math>$approx$ </tex-math></inline-formula>3500 S<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>m<sup>1</sup>) than the 6B-grade graphite paint (<inline-formula> <tex-math>$approx$ </tex-math></inline-formula>2400 S<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>m<sup>−1</sup>). The difference in Seebeck coefficients of all materials demonstrates graphite-dependent tunable transport behavior. After that, flexible thermocouples were fabricated using FLG traces and graphite paints. It exhibited a maximum sensitivity of <inline-formula> <tex-math>$approx$ </tex-math></inline-formula><inline-formula> <tex-math>$37~mu $ </tex-math></inline-formula>V<inline-formula> <tex-math>$cdot $ </tex-math></inline-formula>K<sup>−1</sup> along with rapid response, repeatability, and mechanical stability. This work demonstrates a facile, scalable, and environmentally benign strategy for developing fully carbon-based disposable thermocouples without the need for metals, vacuum process, or complex fabrication process. The results offer a sustainable, low-cost pathway toward precise and eco-friendly thermal sensing technologies for development in wearable technologies.","PeriodicalId":100623,"journal":{"name":"IEEE Journal on Flexible Electronics","volume":"5 9","pages":"346-354"},"PeriodicalIF":0.0,"publicationDate":"2026-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148903191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design Perspective and Numerical Analysis of Eco-Friendly CsGeI3 Perovskite Solar Cell","authors":"Dolly Kumari;Saurabh Kumar Pandey","doi":"10.1109/JFLEX.2026.3686049","DOIUrl":"https://doi.org/10.1109/JFLEX.2026.3686049","url":null,"abstract":"The growing need for clean and reliable energy solutions has accelerated interest in lead-free perovskite photovoltaics (PVs). Cesium germanium iodide (CsGeI<sub>3</sub>) is a promising absorber owing to its suitable bandgap, strong light absorption, and environmentally benign composition. This study numerically analyzes a CsGeI<sub>3</sub>-based perovskite solar cell (PSC) with the structure FTO/TiO<sub>2</sub>/CsGeI<sub>3</sub>/MoS<sub>2</sub>/Ni using the SCAPS-1D simulator. The simulation model is first validated against reported experimental data and subsequently used then to optimize different key parameters, which include electron transport layer (ETL) and hole transport layer (HTL) thickness, absorber thickness, defect densities, interface capture cross sections, and series resistance. The analysis reveals that minimizing interfacial defects and carrier capture cross sections is significantly essential as it affects carrier lifetime and leads to nonradiative losses, while an optimized ETL thickness of <inline-formula> <tex-math>$0.05~mu $ </tex-math></inline-formula>m and absorber thickness of <inline-formula> <tex-math>$6.68~mu $ </tex-math></inline-formula>m maximize charge extraction and light absorption. Under fully optimized conditions, the proposed structure attains an efficiency of 25.02%. These results provide a pathway toward high-efficiency, lead-free perovskite PVs.","PeriodicalId":100623,"journal":{"name":"IEEE Journal on Flexible Electronics","volume":"5 8","pages":"304-311"},"PeriodicalIF":0.0,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148666920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Fully Integrated Output-Capacitorless LDO Regulator With Gain-Boosted Error Amplifier Using 600-nm IGZO TFTs for Integrated Flexible Electronics","authors":"Muhammad Dawood Asghar;Mohit Dandekar;Kris Myny","doi":"10.1109/JFLEX.2026.3686754","DOIUrl":"https://doi.org/10.1109/JFLEX.2026.3686754","url":null,"abstract":"This article presents a fully integrated, output capacitorless (FOCL) low-dropout (LDO) voltage regulator design made with 600-nm amorphous indium–gallium–zinc-oxide (IGZO) thin-film transistor (TFT) on-foil technology that offers only n-channel devices. To compensate for the inherently low transconductance of IGZO TFTs, the proposed LDO integrates a gain-boosted error amplifier (EA) using only n-channel devices and integrated resistors, achieving a simulated DC gain of 72 dB. The regulator attains a line regulation of 2 mV/V and load regulation of 0.75 mV/mA while drawing a low quiescent current (<inline-formula> <tex-math>$boldsymbol {I_{Q}}$ </tex-math></inline-formula>) of <inline-formula> <tex-math>$7.3~boldsymbol {mu }$ </tex-math></inline-formula>A at 3-V input voltage (<inline-formula> <tex-math>$boldsymbol {V_{IN}}$ </tex-math></inline-formula>). The manufactured design shows a high power-supply rejection ratio (PSRR) of 53 dB up to 1-kHz frequency range. The proposed LDO exhibits a settling time of <inline-formula> <tex-math>$63~boldsymbol {mu }$ </tex-math></inline-formula>s when responding to a load transient (<inline-formula> <tex-math>$boldsymbol {Delta I_{LOAD}}$ </tex-math></inline-formula>) of 1–50 mA, while maintaining stability with a phase margin (PM) exceeding 86°. The FOCL-LDO achieves a <inline-formula> <tex-math>$330times $ </tex-math></inline-formula> better figure-of-merit (FoM) compared to previously published IGZO-based LDO designs, demonstrating its potential for fully integrated and power-management solutions in flexible integrated circuits.","PeriodicalId":100623,"journal":{"name":"IEEE Journal on Flexible Electronics","volume":"5 8","pages":"287-295"},"PeriodicalIF":0.0,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11494001","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148666912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design and Optimization of a Grating-Structured Triboelectric Nanogenerator-Based Self-Powered Flexible Pressure Sensor","authors":"Neeraj;Navneet Gupta","doi":"10.1109/JFLEX.2026.3683014","DOIUrl":"https://doi.org/10.1109/JFLEX.2026.3683014","url":null,"abstract":"Triboelectric nanogenerator (TENG)-based self-powered flexible pressure sensors (SPFPSs) have attracted significant attention in healthcare monitoring, human–machine interfaces (HMIs), electronic skin, and intelligent robots. In this investigation, we primarily focused on enhancing the performance of the TENG-based SPFPSs on dielectric-to-dielectric contact separation mode. A TENG-based SPFPS with a grating structure was designed using the finite element method (FEM)-based COMSOL Multiphysics 6.0. A grating structure of triboelectric layers is employed and investigated its impact on the performance of the proposed sensor. Polydimethylsiloxane (PDMS) and nylon are used as tribonegative and tribopositive layers, respectively. The performance of the proposed grating-structured sensor was compared with that of a conventional planar configuration. The results reveal an enhancement factor of 2.16 in the electrical potential within the pressure range of 0–3000 Pa, primarily attributed to the increased effective surface contact area provided by the grating structure. These findings highlight that the investigated proposed sensor has potential for flexible wearable devices in smart healthcare monitoring, physiological signal monitoring, soft robotics, and sports monitoring.","PeriodicalId":100623,"journal":{"name":"IEEE Journal on Flexible Electronics","volume":"5 8","pages":"296-303"},"PeriodicalIF":0.0,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11479185","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148666913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"IEEE Journal on Flexible Electronics Call for Papers: Special Issue on Selected Papers from the IEEE International Conference on Flexible, Printable, Sensors and Systems (FLEPS 2026)","authors":"","doi":"10.1109/JFLEX.2026.3714983","DOIUrl":"https://doi.org/10.1109/JFLEX.2026.3714983","url":null,"abstract":"","PeriodicalId":100623,"journal":{"name":"IEEE Journal on Flexible Electronics","volume":"5 8","pages":"321-321"},"PeriodicalIF":0.0,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11641343","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148666916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Fully Integrated Output-Capacitorless LDO Regulator With Gain-Boosted Error Amplifier Using 600-nm IGZO TFTs for Integrated Flexible Electronics","authors":"Muhammad Dawood Asghar;Mohit Dandekar;Kris Myny","doi":"10.1109/JFLEX.2026.3686754","DOIUrl":"https://doi.org/10.1109/JFLEX.2026.3686754","url":null,"abstract":"This article presents a fully integrated, output capacitorless (FOCL) low-dropout (LDO) voltage regulator design made with 600-nm amorphous indium–gallium–zinc-oxide (IGZO) thin-film transistor (TFT) on-foil technology that offers only n-channel devices. To compensate for the inherently low transconductance of IGZO TFTs, the proposed LDO integrates a gain-boosted error amplifier (EA) using only n-channel devices and integrated resistors, achieving a simulated DC gain of 72 dB. The regulator attains a line regulation of 2 mV/V and load regulation of 0.75 mV/mA while drawing a low quiescent current (<inline-formula> <tex-math>$boldsymbol {I_{Q}}$ </tex-math></inline-formula>) of <inline-formula> <tex-math>$7.3~boldsymbol {mu }$ </tex-math></inline-formula>A at 3-V input voltage (<inline-formula> <tex-math>$boldsymbol {V_{IN}}$ </tex-math></inline-formula>). The manufactured design shows a high power-supply rejection ratio (PSRR) of 53 dB up to 1-kHz frequency range. The proposed LDO exhibits a settling time of <inline-formula> <tex-math>$63~boldsymbol {mu }$ </tex-math></inline-formula>s when responding to a load transient (<inline-formula> <tex-math>$boldsymbol {Delta I_{LOAD}}$ </tex-math></inline-formula>) of 1–50 mA, while maintaining stability with a phase margin (PM) exceeding 86°. The FOCL-LDO achieves a <inline-formula> <tex-math>$330times $ </tex-math></inline-formula> better figure-of-merit (FoM) compared to previously published IGZO-based LDO designs, demonstrating its potential for fully integrated and power-management solutions in flexible integrated circuits.","PeriodicalId":100623,"journal":{"name":"IEEE Journal on Flexible Electronics","volume":"5 8","pages":"287-295"},"PeriodicalIF":0.0,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11494001","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148666926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kyle van Oosterhout;Martijn Timmermans;Marco Fattori;Eugenio Cantatore
{"title":"Analytical Evaluation of Design Tradeoffs in Noise Reduction Techniques for Flexible Electronics","authors":"Kyle van Oosterhout;Martijn Timmermans;Marco Fattori;Eugenio Cantatore","doi":"10.1109/JFLEX.2026.3686769","DOIUrl":"https://doi.org/10.1109/JFLEX.2026.3686769","url":null,"abstract":"Thin-film transistors (TFTs) manufactured on flexible substrates are known to exhibit significant low-frequency noise, which poses challenges for their use in low-noise applications such as biosignal acquisition. Due to the temporal correlation inherent in low-frequency noise sources, techniques like chopping, autozeroing, and correlated double sampling (CDS) can be employed to mitigate 1/f noise; an approach well-established in conventional silicon-complementary metal-oxide semiconductor (Si-CMOS) circuit architectures. However, directly applying these methods to TFT-based designs is not straightforward, as the distinct device physics of TFTs introduces unique design tradeoffs. This work presents an analytical investigation of these tradeoffs for a commercial a-IGZO TFT technology on a flexible substrate. It offers a set of equations that clarify the performance limits and design considerations for implementing noise reduction techniques in TFT circuits, showing it is most noise-efficient to use the minimal switching frequency of the noise reduction technique that satisfies the noise requirements. Furthermore, while chopping is the easiest technique to implement and very effective, it reduces the input impedance of the system the most, while with autozeroing, the input impedance can be kept high but at the cost of a reduced gain in the first stage. The analysis is particularly relevant for biomedical applications, where low-noise performance is critical.","PeriodicalId":100623,"journal":{"name":"IEEE Journal on Flexible Electronics","volume":"5 8","pages":"312-320"},"PeriodicalIF":0.0,"publicationDate":"2026-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148666922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}