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Efficient Network Flow Based Min-cut Balanced Partitioning 基于高效网络流的最小割均衡分区
ICCAD. IEEE/ACM International Conference on Computer-Aided Design Pub Date : 1994-11-06 DOI: 10.1109/ICCAD.1994.629743
Hannah Honghua Yang, Martin D. F. Wong
{"title":"Efficient Network Flow Based Min-cut Balanced Partitioning","authors":"Hannah Honghua Yang, Martin D. F. Wong","doi":"10.1109/ICCAD.1994.629743","DOIUrl":"https://doi.org/10.1109/ICCAD.1994.629743","url":null,"abstract":"We consider the problem of bipartitioning a circuit into two balanced components that minimizes the number of crossing nets. Previously, the Kernighan and Lin type (K&L) heuristics, the simulated annealing approach, and the spectral method were given to solve the problem. However, network flow techniques were overlooked as a viable approach to min-cut balanced bipartition to due its high complexity. In this paper we propose a balanced bipartition heuristic based on repeated max-flow min-cut techniques, and give an efficient implementation that has the same asymptotic time complexity as that of one max-flow computation. We implemented our heuristic algorithm in a package called FBB. The experimental results demonstrate that FBB outperforms the K&L heuristics and the spectral method in terms of the number of crossing nets, and the efficient implementation makes it possible to partition large, circuit instances with reasonable runtime. For example, the average elapsed time for bipartitioning a circuit S35932 of almost 20K gates is less than 20 minutes.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":"28 7 1","pages":"50-55"},"PeriodicalIF":0.0,"publicationDate":"1994-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88896654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 157
Dynamical Identification Of Critical Paths For Iterative Gate Sizing 闸门迭代定径关键路径的动力学辨识
ICCAD. IEEE/ACM International Conference on Computer-Aided Design Pub Date : 1994-11-06 DOI: 10.1109/ICCAD.1994.629855
How-Rern Lin, TingTing Hwang
{"title":"Dynamical Identification Of Critical Paths For Iterative Gate Sizing","authors":"How-Rern Lin, TingTing Hwang","doi":"10.1109/ICCAD.1994.629855","DOIUrl":"https://doi.org/10.1109/ICCAD.1994.629855","url":null,"abstract":"Since only sensitizable paths contribute to the delay of a circuit, false paths must be excluded in optimizing the delay of the circuit. Just identifying false paths in the first place is not sufficient since during iterative optimization process, false paths may become sensitizable, and sensitizable paths false. In this paper, we examine cases for false path becoming sensitizable and sensitizable becoming false. Based on these conditions, we adopt a so-called loose sensitization criterion which is used to develop an algorithm for dynamically identification of sensitizable paths. By combining gate sizing and dynamically identification of sensitizable paths, an efficient performance optimization tool is developed. Results on a set of circuits from ISCAS benchmark set demonstrate that our tool is indeed very effective in reducing circuit delay with less number of gate sized as compared with other methods.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":"45 1","pages":"481-484"},"PeriodicalIF":0.0,"publicationDate":"1994-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91201812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Performance-driven Synthesis Of Asynchronous Controllers 性能驱动的异步控制器综合
ICCAD. IEEE/ACM International Conference on Computer-Aided Design Pub Date : 1994-11-06 DOI: 10.1109/ICCAD.1994.629875
K. Yun, Bill Lin, D. Dill, S. Devadas
{"title":"Performance-driven Synthesis Of Asynchronous Controllers","authors":"K. Yun, Bill Lin, D. Dill, S. Devadas","doi":"10.1109/ICCAD.1994.629875","DOIUrl":"https://doi.org/10.1109/ICCAD.1994.629875","url":null,"abstract":"We examine the implications of a new hazard-free combinational logic synthesis method, which generates multiplexor trees from binary decision diagrams (BDDs)—representations of logic functions factored recursively with respect to input variables—on extended burst-mode asynchronous synthesis. First, the use of the BDD-based synthesis reduces the constraints on state minimization and assignment, which reduces the number of additional state variables required in many cases. Second, in cases where conditional signals are sampled, it eliminates the need for state variable changes preceding output changes, which reduces overall input to output latency. Third, selection variables can easily be ordered to minimize the latency on a user-specified path, which is important for optimizing the performance of systems that use asynchronous components. We present extensive evaluations showing that, with only minimal optimization, the BBD-based synthesis gives comparable results in area with our previous exact two-level synthesis method. We also give a detailed example of the specified path optimization.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":"33 1","pages":"550-557"},"PeriodicalIF":0.0,"publicationDate":"1994-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83124159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A Fast And Memory-efficient Diagnostic Fault Simulation For Sequential Circuits 时序电路快速高效故障诊断仿真
ICCAD. IEEE/ACM International Conference on Computer-Aided Design Pub Date : 1994-11-06 DOI: 10.1109/ICCAD.1994.629903
J. Jou, Shung-Chih Chen
{"title":"A Fast And Memory-efficient Diagnostic Fault Simulation For Sequential Circuits","authors":"J. Jou, Shung-Chih Chen","doi":"10.1109/ICCAD.1994.629903","DOIUrl":"https://doi.org/10.1109/ICCAD.1994.629903","url":null,"abstract":"In this paper, a fast and memory-efficient diagnostic fault simulator for sequential circuits is proposed. In it, a two-level optimization technique is developed and used to prompt the processing speed. In the first high level, an efficient list, which stores the indistinguishable faults so far for each fault during simulation, and the list maintaining algorithm are applied, thus the number of diagnostic comparisons is minimized. In the second low level, a bit-parallel comparison is developed to speed up the comparing process. Therefore, the different diagnostic measure reports for a given test set can be generated very quickly. In addition, the simulator is extended to diagnose the single stuck-at device fault. Experimental results show that this diagnostic simulator achieves a significant speedup compared to previous methods.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":"80 1","pages":"723-726"},"PeriodicalIF":0.0,"publicationDate":"1994-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82271073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Provably Correct High-level Timing Analysis Without Path Sensitization 可证明正确的高级时序分析没有路径敏化
ICCAD. IEEE/ACM International Conference on Computer-Aided Design Pub Date : 1994-11-06 DOI: 10.1109/ICCAD.1994.629905
S. Bhattacharya, S. Dey, F. Brglez
{"title":"Provably Correct High-level Timing Analysis Without Path Sensitization","authors":"S. Bhattacharya, S. Dey, F. Brglez","doi":"10.1109/ICCAD.1994.629905","DOIUrl":"https://doi.org/10.1109/ICCAD.1994.629905","url":null,"abstract":"This paper addresses the problem of true delay estimation during high level design. The existing delay estimation techniques either estimate the topological delay of the circuit which may be pessimistic, or use gate-level timing analysis for calculating the true delay, which may be prohibitively expensive.\u0000We show that the paths in the implementation of a behavioral specification can be partitioned into two sets, SP and UP. While the paths in SP can affect the delay of the circuit, the paths in UP cannot. Consequently, the true delay of the resulting circuit can be computed by just measuring the topological delay of the paths in SP, eliminating the need for the computationally intensive process of path sensitization. Experimental results show that high-level true delay estimation can be done very fast, even when gate-level true delay estimation becomes computationally infeasible. The high-level delay estimates are verified by comparing with delay estimates obtained by gate-level timing analysis on the actual implementation.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":"106 1","pages":"736-742"},"PeriodicalIF":0.0,"publicationDate":"1994-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87829548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
A Symbolic Method To Reduce Power Consumption Of Circuits Containing False Paths 一种降低含假路径电路功耗的符号方法
ICCAD. IEEE/ACM International Conference on Computer-Aided Design Pub Date : 1994-11-06 DOI: 10.1109/ICCAD.1994.629820
R. I. Bahar, G. Hachtel, E. Macii, F. Somenzi
{"title":"A Symbolic Method To Reduce Power Consumption Of Circuits Containing False Paths","authors":"R. I. Bahar, G. Hachtel, E. Macii, F. Somenzi","doi":"10.1109/ICCAD.1994.629820","DOIUrl":"https://doi.org/10.1109/ICCAD.1994.629820","url":null,"abstract":"Power dissipation in technology mapped circuits can be reduced by performing gate re-sizing. Recently we have proposed a symbolic procedure which exploits the compactness of the ADD data structure to accurately calculate the arrival times at each node of a circuit for any primary input vector. In this paper we extend our timing analysis tool to the symbolic calculation of required times and slacks, and we use this information to identify gates of the circuits that can be re-sized. The nice feature of our approach is that it takes into account the presence of false paths naturally. As shown by the experimental results, circuits re-synthesized with the technique we present in this paper are guaranteed to be at least as fast as the original implementations, but smaller and substantially less power-consuming.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":"125 1","pages":"368-371"},"PeriodicalIF":0.0,"publicationDate":"1994-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86580222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
Delay And Area Optimization For Compact Placement By Gate Resizing And Relocation 通过栅极调整和重新定位实现紧凑布局的延迟和面积优化
ICCAD. IEEE/ACM International Conference on Computer-Aided Design Pub Date : 1994-11-06 DOI: 10.1109/ICCAD.1994.629757
Weitong Chuang, I. Hajj
{"title":"Delay And Area Optimization For Compact Placement By Gate Resizing And Relocation","authors":"Weitong Chuang, I. Hajj","doi":"10.1109/ICCAD.1994.629757","DOIUrl":"https://doi.org/10.1109/ICCAD.1994.629757","url":null,"abstract":"In this paper, we first present an efficient algorithm for the gate sizing problem. Then we propose an algorithm which performs delay and area optimization for a given compact placement by resizing and relocating cells in the circuit layout. Since the gate sizing procedure is embedded within the placement adjustment process, interconnect capacitance information is included in the gate size selection process. As a result, the algorithm is able to obtain superior solutions.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":"126 1","pages":"145-148"},"PeriodicalIF":0.0,"publicationDate":"1994-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80384097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Symmetry Detection And Dynamic Variable 对称检测和动态变量
ICCAD. IEEE/ACM International Conference on Computer-Aided Design Pub Date : 1994-11-06 DOI: 10.1109/ICCAD.1994.629887
Shipra Panda, F. Somenzi, B. Plessier
{"title":"Symmetry Detection And Dynamic Variable","authors":"Shipra Panda, F. Somenzi, B. Plessier","doi":"10.1109/ICCAD.1994.629887","DOIUrl":"https://doi.org/10.1109/ICCAD.1994.629887","url":null,"abstract":"Knowing that some variables are symmetric in a function has numerous applications; in particular, it can help produce better variable orders for Binary Decision Diagrams (BDDs) and related data structures (e.g., Algebraic Decision Diagrams). It has been conjectured that there always exists an optimum order for a BDD wherein symmetric variables are contiguous. We propose a new algorithm for the detection of symmetries, based on dynamic reordering, and we study its interaction with the reordering algorithm itself. We show that combining sifting with an efficient symmetry check for contiguous variables results in the fastest symmetry detection algorithm reported to date and produces better variable orders for many BDDs. The overhead on the sifting algorithm is negligible.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":"172 1","pages":"628-631"},"PeriodicalIF":0.0,"publicationDate":"1994-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77517225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Clock Period Constrained Minimal Buffer Insertion In Clock Trees 时钟周期约束的最小缓冲区插入时钟树
ICCAD. IEEE/ACM International Conference on Computer-Aided Design Pub Date : 1994-11-06 DOI: 10.1109/ICCAD.1994.629769
G. Téllez, M. Sarrafzadeh
{"title":"Clock Period Constrained Minimal Buffer Insertion In Clock Trees","authors":"G. Téllez, M. Sarrafzadeh","doi":"10.1109/ICCAD.1994.629769","DOIUrl":"https://doi.org/10.1109/ICCAD.1994.629769","url":null,"abstract":"In this paper we investigate the problem of computing a lower bound on the number of buffers required when given a maximum clock frequency and a predefined clock tree. Using generalized properties of published CMOS timing models, we formulate a novel non-linear and a simplified linear buffer insertion problem. We solve the latter optimally with an O(n) algorithm. The basic formulation and algorithm are extended to include a skew upper bound constraint. Using these algorithms we propose further algorithmic extensions that allow area and phase delay tradeoffs. Our results are verified using SPICE3e2 simulations with MCNC MOSIS 2.0μ models and parameters. Experiments show our buffer insertion algorithms can be used effectively for high-speed clock designs.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":"12 1","pages":"219-223"},"PeriodicalIF":0.0,"publicationDate":"1994-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78560882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Synthesis Of Manufacturable Analog Circuits 可制造模拟电路的合成
ICCAD. IEEE/ACM International Conference on Computer-Aided Design Pub Date : 1994-11-06 DOI: 10.1109/ICCAD.1994.629880
T. Mukherjee, L. Carley, Rob A. Rutenbar
{"title":"Synthesis Of Manufacturable Analog Circuits","authors":"T. Mukherjee, L. Carley, Rob A. Rutenbar","doi":"10.1109/ICCAD.1994.629880","DOIUrl":"https://doi.org/10.1109/ICCAD.1994.629880","url":null,"abstract":"We describe a synthesis system that takes operating range constraints and inter- and intra-circuit parametric manufacturing variations into account while designing a sized and biased analog circuit. Previous approaches to CAD for analog circuit synthesis have concentrated on nominal analog circuit design, and subsequent optimization of these circuits for statistical fluctuations and operating point ranges. Our approach simultaneously synthesizes and optimizes for operating and manufacturing variations by mapping the circuit design problem into an Infinite Programming problem and solving it using an annealing within annealing formulation. We present circuits designed by this integrated synthesis system, and show that they indeed meet their operating range and parametric manufacturing constraints.","PeriodicalId":90518,"journal":{"name":"ICCAD. IEEE/ACM International Conference on Computer-Aided Design","volume":"131 1","pages":"586-593"},"PeriodicalIF":0.0,"publicationDate":"1994-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77363683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
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