ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems最新文献_第8页

PowerNap: eliminating server idle power PowerNap:消除服务器闲置电源

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2009-03-07 DOI: 10.1145/1508244.1508269

David Meisner, Brian T. Gold, T. Wenisch

{"title":"PowerNap: eliminating server idle power","authors":"David Meisner, Brian T. Gold, T. Wenisch","doi":"10.1145/1508244.1508269","DOIUrl":"https://doi.org/10.1145/1508244.1508269","url":null,"abstract":"Data center power consumption is growing to unprecedented levels: the EPA estimates U.S. data centers will consume 100 billion kilowatt hours annually by 2011. Much of this energy is wasted in idle systems: in typical deployments, server utilization is below 30%, but idle servers still consume 60% of their peak power draw. Typical idle periods though frequent--last seconds or less, confounding simple energy-conservation approaches.\u0000 In this paper, we propose PowerNap, an energy-conservation approach where the entire system transitions rapidly between a high-performance active state and a near-zero-power idle state in response to instantaneous load. Rather than requiring fine-grained power-performance states and complex load-proportional operation from each system component, PowerNap instead calls for minimizing idle power and transition time, which are simpler optimization goals. Based on the PowerNap concept, we develop requirements and outline mechanisms to eliminate idle power waste in enterprise blade servers. Because PowerNap operates in low-efficiency regions of current blade center power supplies, we introduce the Redundant Array for Inexpensive Load Sharing (RAILS), a power provisioning approach that provides high conversion efficiency across the entire range of PowerNap's power demands. Using utilization traces collected from enterprise-scale commercial deployments, we demonstrate that, together, PowerNap and RAILS reduce average server power consumption by 74%.","PeriodicalId":89892,"journal":{"name":"ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems","volume":"46 1","pages":"205-216"},"PeriodicalIF":0.0,"publicationDate":"2009-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76171895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1019

Leak pruning 泄漏修剪

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2009-03-01 DOI: 10.1145/1508244.1508277

Michael D. Bond, K. McKinley

{"title":"Leak pruning","authors":"Michael D. Bond, K. McKinley","doi":"10.1145/1508244.1508277","DOIUrl":"https://doi.org/10.1145/1508244.1508277","url":null,"abstract":"Managed languages improve programmer productivity with type safety and garbage collection, which eliminate memory errors such as dangling pointers, double frees, and buffer overflows. However, because garbage collection uses reachability to over-approximate live objects, programs may still leak memory if programmers forget to eliminate the last reference to an object that will not be used again. Leaks slow programs by increasing collector workload and frequency. Growing leaks eventually crash programs.\u0000 This paper introduces leak pruning, which keeps programs running by predicting and reclaiming leaked objects at run time. It predicts dead objects and reclaims them based on observing data structure usage patterns. Leak pruning preserves semantics because it waits for heap exhaustion before reclaiming objects and poisons references to objects it reclaims. If the program later tries to access a poisoned reference, the virtual machine (VM) throws an error. We show leak pruning has low overhead in a Java VM and evaluate it on 10 leaking programs. Leak pruning does not help two programs, executes five substantial programs 1.6-81X longer, and executes three programs, including a leak in Eclipse, for at least 24 hours. In the worst case, leak pruning defers fatal errors. In the best case, it keeps leaky programs running with preserved semantics and consistent throughput.","PeriodicalId":89892,"journal":{"name":"ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems","volume":"55 1","pages":"277-288"},"PeriodicalIF":0.0,"publicationDate":"2009-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89116489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 55

TwinDrivers: semi-automatic derivation of fast and safe hypervisor network drivers from guest OS drivers TwinDrivers:从客户操作系统驱动程序中半自动派生快速和安全的hypervisor网络驱动程序

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2009-03-01 DOI: 10.1145/1508244.1508279

Aravind Menon, Simon Schubert, W. Zwaenepoel

{"title":"TwinDrivers: semi-automatic derivation of fast and safe hypervisor network drivers from guest OS drivers","authors":"Aravind Menon, Simon Schubert, W. Zwaenepoel","doi":"10.1145/1508244.1508279","DOIUrl":"https://doi.org/10.1145/1508244.1508279","url":null,"abstract":"In a virtualized environment, device drivers are often run inside a virtual machine (VM) rather than in the hypervisor, for reasons of safety and reduction in software engineering effort. Unfortunately, this approach results in poor performance for I/O-intensive devices such as network cards. The alternative approach of running device drivers directly in the hypervisor yields better performance, but results in the loss of safety guarantees for the hypervisor and incurs additional software engineering costs.\u0000 In this paper we present TwinDrivers, a framework which allows us to semi-automatically create safe and efficient hypervisor drivers from guest OS drivers. The hypervisor driver runs directly in the hypervisor, but its data resides completely in the driver VM address space. A Software Virtual Memory mechanism allows the driver to access its VM data efficiently from the hypervisor running in any guest context, and also protects the hypervisor from invalid memory accesses from the driver. An upcall mechanism allows the hypervisor to largely reuse the driver support infrastructure present in the VM. The TwinDriver system thus combines most of the performance benefits of hypervisor-based driver approaches with the safety and software engineering benefits of VM-based driver approaches.\u0000 Using the TwinDrivers hypervisor driver, we are able to improve the guest domain networking throughput in Xen by a factor of 2.4 for transmit workloads, and 2.1 for receive workloads, both in CPU-scaled units, and achieve close to 64-67 of native Linux throughput.","PeriodicalId":89892,"journal":{"name":"ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems","volume":"2 1","pages":"301-312"},"PeriodicalIF":0.0,"publicationDate":"2009-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80753441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 35

Per-thread cycle accounting in SMT processors SMT处理器中的每个线程周期记帐

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2009-03-01 DOI: 10.1145/1508244.1508260

Stijn Eyerman, L. Eeckhout

{"title":"Per-thread cycle accounting in SMT processors","authors":"Stijn Eyerman, L. Eeckhout","doi":"10.1145/1508244.1508260","DOIUrl":"https://doi.org/10.1145/1508244.1508260","url":null,"abstract":"This paper proposes a cycle accounting architecture for Simultaneous Multithreading (SMT) processors that estimates the execution times for each of the threads had they been executed alone, while they are running simultaneously on the SMT processor. This is done by accounting each cycle to either a base, miss event or waiting cycle component during multi-threaded execution. Single-threaded alone execution time is then estimated as the sum of the base and miss event components; the waiting cycle component represents the lost cycle count due to SMT execution. The cycle accounting architecture incurs reasonable hardware cost (around 1KB of storage) and estimates single-threaded performance with average prediction errors around 7.2% for two-program workloads and 11.7% for four-program workloads.\u0000 The cycle accounting architecture has several important applications to system software and its interaction with SMT hardware. For one, the estimated single-thread alone execution time provides an accurate picture to system software of the actually consumed processor cycles per thread. The alone execution time instead of the total execution time (timeslice) may make system software scheduling policies more effective. Second, a new class of thread-progress aware SMT fetch policies based on per-thread progress indicators enable system software level priorities to be enforced at the hardware level.","PeriodicalId":89892,"journal":{"name":"ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems","volume":"12 1","pages":"133-144"},"PeriodicalIF":0.0,"publicationDate":"2009-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91287040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 67

Early experience with a commercial hardware transactional memory implementation 有商业硬件事务性内存实现的早期经验

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2009-03-01 DOI: 10.1145/1508244.1508263

D. Dice, Yossi Lev, Mark Moir, Daniel Nussbaum

引用次数: 291

Gordon: using flash memory to build fast, power-efficient clusters for data-intensive applications Gordon:使用闪存为数据密集型应用程序构建快速、节能的集群

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2009-03-01 DOI: 10.1145/1508244.1508270

Adrian M. Caulfield, Laura M. Grupp, S. Swanson

{"title":"Gordon: using flash memory to build fast, power-efficient clusters for data-intensive applications","authors":"Adrian M. Caulfield, Laura M. Grupp, S. Swanson","doi":"10.1145/1508244.1508270","DOIUrl":"https://doi.org/10.1145/1508244.1508270","url":null,"abstract":"As our society becomes more information-driven, we have begun to amass data at an astounding and accelerating rate. At the same time, power concerns have made it difficult to bring the necessary processing power to bear on querying, processing, and understanding this data. We describe Gordon, a system architecture for data-centric applications that combines low-power processors, flash memory, and data-centric programming systems to improve performance for data-centric applications while reducing power consumption. The paper presents an exhaustive analysis of the design space of Gordon systems, focusing on the trade-offs between power, energy, and performance that Gordon must make. It analyzes the impact of flash-storage and the Gordon architecture on the performance and power efficiency of data-centric applications. It also describes a novel flash translation layer tailored to data intensive workloads and large flash storage arrays. Our data show that, using technologies available in the near future, Gordon systems can out-perform disk-based clusters by 1.5× and deliver up to 2.5× more performance per Watt.","PeriodicalId":89892,"journal":{"name":"ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems","volume":"39 1","pages":"217-228"},"PeriodicalIF":0.0,"publicationDate":"2009-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83579621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 280

Accelerating critical section execution with asymmetric multi-core architectures 非对称多核架构加速临界区执行

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2009-03-01 DOI: 10.1145/1508244.1508274

M. A. Suleman, O. Mutlu, Moinuddin K. Qureshi, Y. Patt

{"title":"Accelerating critical section execution with asymmetric multi-core architectures","authors":"M. A. Suleman, O. Mutlu, Moinuddin K. Qureshi, Y. Patt","doi":"10.1145/1508244.1508274","DOIUrl":"https://doi.org/10.1145/1508244.1508274","url":null,"abstract":"To improve the performance of a single application on Chip Multiprocessors (CMPs), the application must be split into threads which execute concurrently on multiple cores. In multi-threaded applications, critical sections are used to ensure that only one thread accesses shared data at any given time. Critical sections can serialize the execution of threads, which significantly reduces performance and scalability.\u0000 This paper proposes Accelerated Critical Sections (ACS), a technique that leverages the high-performance core(s) of an Asymmetric Chip Multiprocessor (ACMP) to accelerate the execution of critical sections. In ACS, selected critical sections are executed by a high-performance core, which can execute the critical section faster than the other, smaller cores. As a result, ACS reduces serialization: it lowers the likelihood of threads waiting for a critical section to finish. Our evaluation on a set of 12 critical-section-intensive workloads shows that ACS reduces the average execution time by 34% compared to an equal-area 32T-core symmetric CMP and by 23% compared to an equal-area ACMP. Moreover, for 7 out of the 12 workloads, ACS improves scalability by increasing the number of threads at which performance saturates.","PeriodicalId":89892,"journal":{"name":"ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems","volume":"21 1","pages":"253-264"},"PeriodicalIF":0.0,"publicationDate":"2009-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75482022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 321

Architectural support for SWAR text processing with parallel bit streams: the inductive doubling principle 对并行比特流的SWAR文本处理的体系结构支持:归纳加倍原理

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2009-03-01 DOI: 10.1145/1508244.1508283

R. Cameron, Dan Lin

引用次数: 19

CTrigger: exposing atomicity violation bugs from their hiding places CTrigger:从隐藏的地方暴露原子性冲突bug

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2009-03-01 DOI: 10.1145/1508244.1508249

Soyeon Park, Shan Lu, Yuanyuan Zhou

{"title":"CTrigger: exposing atomicity violation bugs from their hiding places","authors":"Soyeon Park, Shan Lu, Yuanyuan Zhou","doi":"10.1145/1508244.1508249","DOIUrl":"https://doi.org/10.1145/1508244.1508249","url":null,"abstract":"Multicore hardware is making concurrent programs pervasive. Unfortunately, concurrent programs are prone to bugs. Among different types of concurrency bugs, atomicity violation bugs are common and important. Existing techniques to detect atomicity violation bugs suffer from one limitation: requiring bugs to manifest during monitored runs, which is an open problem in concurrent program testing.\u0000 This paper makes two contributions. First, it studies the interleaving characteristics of the common practice in concurrent program testing (i.e., running a program over and over) to understand why atomicity violation bugs are hard to expose. Second, it proposes CTrigger to effectively and efficiently expose atomicity violation bugs in large programs. CTrigger focuses on a special type of interleavings (i.e., unserializable interleavings) that are inherently correlated to atomicity violation bugs, and uses trace analysis to systematically identify (likely) feasible unserializable interleavings with low occurrence-probability. CTrigger then uses minimum execution perturbation to exercise low-probability interleavings and expose difficult-to-catch atomicity violation.\u0000 We evaluate CTrigger with real-world atomicity violation bugs from four sever/desktop applications (Apache, MySQL, Mozilla, and PBZIP2) and three SPLASH2 applications on 8-core machines. CTrigger efficiently exposes the tested bugs within 1--235 seconds, two to four orders of magnitude faster than stress testing. Without CTrigger, some of these bugs do not manifest even after 7 full days of stress testing. In addition, without deterministic replay support, once a bug is exposed, CTrigger can help programmers reliably reproduce it for diagnosis. Our tested bugs are reproduced by CTrigger mostly within 5 seconds, 300 to over 60000 times faster than stress testing.","PeriodicalId":89892,"journal":{"name":"ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems","volume":"6 1","pages":"25-36"},"PeriodicalIF":0.0,"publicationDate":"2009-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86994143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 326

An evaluation of the TRIPS computer system 对TRIPS计算机系统的评价

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2009-03-01 DOI: 10.1145/1508244.1508246

Mark Gebhart, Bertrand A. Maher, Katherine E. Coons, Jeff Diamond, Paul V. Gratz, M. Marino, N. Ranganathan, Behnam Robatmili, Aaron Smith, J. Burrill, S. Keckler, D. Burger, K. McKinley

{"title":"An evaluation of the TRIPS computer system","authors":"Mark Gebhart, Bertrand A. Maher, Katherine E. Coons, Jeff Diamond, Paul V. Gratz, M. Marino, N. Ranganathan, Behnam Robatmili, Aaron Smith, J. Burrill, S. Keckler, D. Burger, K. McKinley","doi":"10.1145/1508244.1508246","DOIUrl":"https://doi.org/10.1145/1508244.1508246","url":null,"abstract":"The TRIPS system employs a new instruction set architecture (ISA) called Explicit Data Graph Execution (EDGE) that renegotiates the boundary between hardware and software to expose and exploit concurrency. EDGE ISAs use a block-atomic execution model in which blocks are composed of dataflow instructions. The goal of the TRIPS design is to mine concurrency for high performance while tolerating emerging technology scaling challenges, such as increasing wire delays and power consumption. This paper evaluates how well TRIPS meets this goal through a detailed ISA and performance analysis. We compare performance, using cycles counts, to commercial processors. On SPEC CPU2000, the Intel Core 2 outperforms compiled TRIPS code in most cases, although TRIPS matches a Pentium 4. On simple benchmarks, compiled TRIPS code outperforms the Core 2 by 10% and hand-optimized TRIPS code outperforms it by factor of 3. Compared to conventional ISAs, the block-atomic model provides a larger instruction window, increases concurrency at a cost of more instructions executed, and replaces register and memory accesses with more efficient direct instruction-to-instruction communication. Our analysis suggests ISA, microarchitecture, and compiler enhancements for addressing weaknesses in TRIPS and indicates that EDGE architectures have the potential to exploit greater concurrency in future technologies.","PeriodicalId":89892,"journal":{"name":"ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems","volume":"73 1","pages":"1-12"},"PeriodicalIF":0.0,"publicationDate":"2009-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84207205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 70