ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems最新文献_第9页

ISOLATOR: dynamically ensuring isolation in comcurrent programs ISOLATOR:动态确保并发程序的隔离

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2009-03-01 DOI: 10.1145/1508244.1508266

S. Rajamani, G. Ramalingam, Venkatesh Prasad Ranganath, K. Vaswani

引用次数: 55

Capo: a software-hardware interface for practical deterministic multiprocessor replay 实用的确定性多处理器重放的软硬件接口

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2009-03-01 DOI: 10.1145/1508244.1508254

Pablo Montesinos, Matthew Hicks, Samuel T. King, J. Torrellas

{"title":"Capo: a software-hardware interface for practical deterministic multiprocessor replay","authors":"Pablo Montesinos, Matthew Hicks, Samuel T. King, J. Torrellas","doi":"10.1145/1508244.1508254","DOIUrl":"https://doi.org/10.1145/1508244.1508254","url":null,"abstract":"While deterministic replay of parallel programs is a powerful technique, current proposals have shortcomings. Specifically, software-based replay systems have high overheads on multiprocessors, while hardware-based proposals focus only on basic hardware-level mechanisms, ignoring the overall replay system. To be practical, hardware-based replay systems need to support an environment with multiple parallel jobs running concurrently -- some being recorded, others being replayed and even others running without recording or replay. Moreover, they need to manage limited-size log buffers.\u0000 This paper addresses these shortcomings by introducing, for the first time, a set of abstractions and a software-hardware interface for practical hardware-assisted replay of multiprocessor systems. The approach, called Capo, introduces the novel abstraction of the Replay Sphere to separate the responsibilities of the hardware and software components of the replay system. In this paper, we also design and build CapoOne, a prototype of a deterministic multiprocessor replay system that implements Capo using Linux and simulated DeLorean hardware. Our evaluation of 4-processor executions shows that CapoOne largely records with the efficiency of hardware-based schemes and the flexibility of software-based schemes.","PeriodicalId":89892,"journal":{"name":"ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems","volume":"142 1","pages":"73-84"},"PeriodicalIF":0.0,"publicationDate":"2009-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77341939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 117

StreamRay: a stream filtering architecture for coherent ray tracing StreamRay:用于相干光线跟踪的流过滤架构

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2009-03-01 DOI: 10.1145/1508244.1508282

K. Ramani, C. Gribble, A. Davis

{"title":"StreamRay: a stream filtering architecture for coherent ray tracing","authors":"K. Ramani, C. Gribble, A. Davis","doi":"10.1145/1508244.1508282","DOIUrl":"https://doi.org/10.1145/1508244.1508282","url":null,"abstract":"The wide availability of commodity graphics processors has made real-time graphics an intrinsic component of the human/computer interface. These graphics cores accelerate the z-buffer algorithm and provide a highly interactive experience at a relatively low cost. However, many applications in entertainment, science, and industry require high quality lighting effects such as accurate shadows, reflection, and refraction. These effects can be difficult to achieve with z-buffer algorithms but are straightforward to implement using ray tracing. Although ray tracing is computationally more complex, the algorithm exhibits excellent scaling and parallelism properties. Nevertheless, ray tracing memory access patterns are difficult to predict and the parallelism speedup promise is therefore hard to achieve.\u0000 This paper highlights a novel approach to ray tracing based on stream filtering and presents StreamRay, a multicore wide SIMD microarchitecture that delivers interactive frame rates of 15-32 frames/second for scenes of high geometric complexity and exhibits high utilization for SIMD widths ranging from eight to 16 elements. StreamRay consists of two main components: the ray engine, which is responsible for stream assembly and employs address generation units that generate addresses to form large SIMD vectors, and the filter engine, which implements the ray tracing operations with programmable accelerators. Results demonstrate that separating address and data processing reduces data movement and resource contention. Performance improves by 56% while simultaneously providing 11.63% power savings per accelerator core compared to a design which does not use separate resources for address and data computations.","PeriodicalId":89892,"journal":{"name":"ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems","volume":"42 1","pages":"325-336"},"PeriodicalIF":0.0,"publicationDate":"2009-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90898368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 31

Recovery domains: an organizing principle for recoverable operating systems 恢复域:可恢复操作系统的组织原则

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2009-02-28 DOI: 10.1145/1508244.1508251

Andrew Lenharth, Vikram S. Adve, Samuel T. King

引用次数: 61

Dynamic prediction of collection yield for managed runtimes 托管运行时的收集产出的动态预测

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2009-02-28 DOI: 10.1145/1508244.1508278

Michal Wegiel, C. Krintz

{"title":"Dynamic prediction of collection yield for managed runtimes","authors":"Michal Wegiel, C. Krintz","doi":"10.1145/1508244.1508278","DOIUrl":"https://doi.org/10.1145/1508244.1508278","url":null,"abstract":"The growth in complexity of modern systems makes it increasingly difficult to extract high-performance. The software stacks for such systems typically consist of multiple layers and include managed runtime environments (MREs). In this paper, we investigate techniques to improve cooperation between these layers and the hardware to increase the efficacy of automatic memory management in MREs.\u0000 General-purpose MREs commonly implement parallel and/or concurrent garbage collection and employ compaction to eliminate heap fragmentation. Moreover, most systems trigger collection based on the amount of heap a program uses. Our analysis shows that in many cases this strategy leads to ineffective collections that are unable to reclaim sufficient space to justify the incurred cost. To avoid such collections, we exploit the observation that dead objects tend to cluster together and form large, never-referenced, regions in the address space that correlate well with virtual pages that have not recently been referenced by the application. We leverage this correlation to design a new, simple and light-weight, yield predictor that estimates the amount of reclaimable space in the heap using hardware page reference bits. Our predictor allows MREs to avoid low-yield collections and thereby improve resource management.\u0000 We integrate this predictor into three state-of-the-art parallel compactors, implemented in the HotSpot JVM, that represent distinct canonical heap layouts. Our empirical evaluation, based on standard Java benchmarks and open-source applications, indicates that inexpensive and accurate yield prediction can improve performance significantly.","PeriodicalId":89892,"journal":{"name":"ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems","volume":"25 1","pages":"289-300"},"PeriodicalIF":0.0,"publicationDate":"2009-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76075980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Mixed-mode multicore reliability 混合模式多核可靠性

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2009-02-28 DOI: 10.1145/1508244.1508265

Philip M. Wells, Koushik Chakraborty, G. Sohi

{"title":"Mixed-mode multicore reliability","authors":"Philip M. Wells, Koushik Chakraborty, G. Sohi","doi":"10.1145/1508244.1508265","DOIUrl":"https://doi.org/10.1145/1508244.1508265","url":null,"abstract":"Future processors are expected to observe increasing rates of hardware faults. Using Dual-Modular Redundancy (DMR), two cores of a multicore can be loosely coupled to redundantly execute a single software thread, providing very high coverage from many difference sources of faults. This reliability, however, comes at a high price in terms of per-thread IPC and overall system throughput.\u0000 We make the observation that a user may want to run both applications requiring high reliability, such as financial software, and more fault tolerant applications requiring high performance, such as media or web software, on the same machine at the same time. Yet a traditional DMR system must fully operate in redundant mode whenever any application requires high reliability.\u0000 This paper proposes a Mixed-Mode Multicore (MMM), which enables most applications, including the system software, to run with high reliability in DMR mode, while applications that need high performance can avoid the penalty of DMR. Though conceptually simple, two key challenges arise: 1) care must be taken to protect reliable applications from any faults occurring to applications running in high performance mode, and 2) the desire to execute additional independent software threads for a performance application complicates the scheduling of computation to cores. After solving these issues, an MMM is shown to improve overall system performance, compared to a traditional DMR system, by approximately 2X when one reliable and one performance application are concurrently executing.","PeriodicalId":89892,"journal":{"name":"ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems","volume":"103 1","pages":"169-180"},"PeriodicalIF":0.0,"publicationDate":"2009-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74858672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 55

Kendo: efficient deterministic multithreading in software 剑道:软件中高效的确定性多线程

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2009-02-28 DOI: 10.1145/1508244.1508256

Marek Olszewski, Jason Ansel, Saman P. Amarasinghe

{"title":"Kendo: efficient deterministic multithreading in software","authors":"Marek Olszewski, Jason Ansel, Saman P. Amarasinghe","doi":"10.1145/1508244.1508256","DOIUrl":"https://doi.org/10.1145/1508244.1508256","url":null,"abstract":"Although chip-multiprocessors have become the industry standard, developing parallel applications that target them remains a daunting task. Non-determinism, inherent in threaded applications, causes significant challenges for parallel programmers by hindering their ability to create parallel applications with repeatable results. As a consequence, parallel applications are significantly harder to debug, test, and maintain than sequential programs.\u0000 This paper introduces Kendo: a new software-only system that provides deterministic multithreading of parallel applications. Kendo enforces a deterministic interleaving of lock acquisitions and specially declared non-protected reads through a novel dynamically load-balanced deterministic scheduling algorithm. The algorithm tracks the progress of each thread using performance counters to construct a deterministic logical time that is used to compute an interleaving of shared data accesses that is both deterministic and provides good load balancing. Kendo can run on today's commodity hardware while incurring only a modest performance cost. Experimental results on the SPLASH-2 applications yield a geometric mean overhead of only 16% when running on 4 processors. This low overhead makes it possible to benefit from Kendo even after an application is deployed. Programmers can start using Kendo today to program parallel applications that are easier to develop, debug, and test.","PeriodicalId":89892,"journal":{"name":"ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems","volume":"7 1","pages":"97-108"},"PeriodicalIF":0.0,"publicationDate":"2009-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85189562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 402

Producing wrong data without doing anything obviously wrong! 在没有做任何明显错误的事情的情况下生成错误的数据!

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2009-02-28 DOI: 10.1145/1508244.1508275

Todd Mytkowicz, Amer Diwan, Matthias Hauswirth, P. Sweeney

{"title":"Producing wrong data without doing anything obviously wrong!","authors":"Todd Mytkowicz, Amer Diwan, Matthias Hauswirth, P. Sweeney","doi":"10.1145/1508244.1508275","DOIUrl":"https://doi.org/10.1145/1508244.1508275","url":null,"abstract":"This paper presents a surprising result: changing a seemingly innocuous aspect of an experimental setup can cause a systems researcher to draw wrong conclusions from an experiment. What appears to be an innocuous aspect in the experimental setup may in fact introduce a significant bias in an evaluation. This phenomenon is called measurement bias in the natural and social sciences.\u0000 Our results demonstrate that measurement bias is significant and commonplace in computer system evaluation. By significant we mean that measurement bias can lead to a performance analysis that either over-states an effect or even yields an incorrect conclusion. By commonplace we mean that measurement bias occurs in all architectures that we tried (Pentium 4, Core 2, and m5 O3CPU), both compilers that we tried (gcc and Intel's C compiler), and most of the SPEC CPU2006 C programs. Thus, we cannot ignore measurement bias. Nevertheless, in a literature survey of 133 recent papers from ASPLOS, PACT, PLDI, and CGO, we determined that none of the papers with experimental results adequately consider measurement bias.\u0000 Inspired by similar problems and their solutions in other sciences, we describe and demonstrate two methods, one for detecting (causal analysis) and one for avoiding (setup randomization) measurement bias.","PeriodicalId":89892,"journal":{"name":"ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems","volume":"1 1","pages":"265-276"},"PeriodicalIF":0.0,"publicationDate":"2009-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88246661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 340

Complete information flow tracking from the gates up 完整的信息流跟踪从大门

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2009-02-28 DOI: 10.1145/1508244.1508258

Mohit Tiwari, Hassan M. G. Wassel, Bita Mazloom, Shashidhar Mysore, F. Chong, T. Sherwood

{"title":"Complete information flow tracking from the gates up","authors":"Mohit Tiwari, Hassan M. G. Wassel, Bita Mazloom, Shashidhar Mysore, F. Chong, T. Sherwood","doi":"10.1145/1508244.1508258","DOIUrl":"https://doi.org/10.1145/1508244.1508258","url":null,"abstract":"For many mission-critical tasks, tight guarantees on the flow of information are desirable, for example, when handling important cryptographic keys or sensitive financial data. We present a novel architecture capable of tracking all information flow within the machine, including all explicit data transfers and all implicit flows (those subtly devious flows caused by not performing conditional operations). While the problem is impossible to solve in the general case, we have created a machine that avoids the general-purpose programmability that leads to this impossibility result, yet is still programmable enough to handle a variety of critical operations such as public-key encryption and authentication. Through the application of our novel gate-level information flow tracking method, we show how all flows of information can be precisely tracked. From this foundation, we then describe how a class of architectures can be constructed, from the gates up, to completely capture all information flows and we measure the impact of doing so on the hardware implementation, the ISA, and the programmer.","PeriodicalId":89892,"journal":{"name":"ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems","volume":"19 1","pages":"109-120"},"PeriodicalIF":0.0,"publicationDate":"2009-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87458160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 232

Maximum benefit from a minimal HTM 以最小的HTM获得最大的收益

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2009-02-28 DOI: 10.1145/1508244.1508262

O. S. Hofmann, C. Rossbach, E. Witchel

引用次数: 25