ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems最新文献_第4页

DeAliaser: alias speculation using atomic region support dealaliaser:别名推测使用原子区域支持

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2013-03-16 DOI: 10.1145/2451116.2451136

Wonsun Ahn, Yuelu Duan, J. Torrellas

{"title":"DeAliaser: alias speculation using atomic region support","authors":"Wonsun Ahn, Yuelu Duan, J. Torrellas","doi":"10.1145/2451116.2451136","DOIUrl":"https://doi.org/10.1145/2451116.2451136","url":null,"abstract":"Alias analysis is a critical component in many compiler optimizations. A promising approach to reduce the complexity of alias analysis is to use speculation. The approach consists of performing optimizations assuming the alias relationships that are true most of the time, and repairing the code when such relationships are found not to hold through runtime checks.\u0000 This paper proposes a general alias speculation scheme that leverages upcoming hardware support for transactions with the help of some ISA extensions. The ability of transactions to checkpoint and roll back frees the compiler to pursue aggressive optimizations without having to worry about recovery code. Also, exposing the memory conflict detection hardware in transactions to software allows runtime checking of aliases with little or no overhead. We test the potential of the novel alias speculation approach with Loop Invariant Code Motion (LICM), Global Value Numbering (GVN), and Partial Redundancy Elimination (PRE) optimization passes. On average, they are shown to reduce program execution time by 9% in SPEC FP2006 applications and 3% in SPEC INT2006 applications over the alias analysis of a state-of-the-art compiler.","PeriodicalId":89892,"journal":{"name":"ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems","volume":"475 1","pages":"167-180"},"PeriodicalIF":0.0,"publicationDate":"2013-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80921945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Computational sprinting on a hardware/software testbed 在硬件/软件测试台上进行计算冲刺

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2013-03-16 DOI: 10.1145/2451116.2451135

Arun Raghavan, Laurel Emurian, Lei Shao, M. Papaefthymiou, K. Pipe, T. Wenisch, Milo M. K. Martin

{"title":"Computational sprinting on a hardware/software testbed","authors":"Arun Raghavan, Laurel Emurian, Lei Shao, M. Papaefthymiou, K. Pipe, T. Wenisch, Milo M. K. Martin","doi":"10.1145/2451116.2451135","DOIUrl":"https://doi.org/10.1145/2451116.2451135","url":null,"abstract":"CMOS scaling trends have led to an inflection point where thermal constraints (especially in mobile devices that employ only passive cooling) preclude sustained operation of all transistors on a chip --- a phenomenon called \"dark silicon.\" Recent research proposed computational sprinting --- exceeding sustainable thermal limits for short intervals --- to improve responsiveness in light of the bursty computation demands of many media-rich interactive mobile applications. Computational sprinting improves responsiveness by activating reserve cores (parallel sprinting) and/or boosting frequency/voltage (frequency sprinting) to power levels that far exceed the system's sustainable cooling capabilities, relying on thermal capacitance to buffer heat.\u0000 Prior work analyzed the feasibility of sprinting through modeling and simulation. In this work, we investigate sprinting using a hardware/software testbed. First, we study unabridged sprints, wherein the computation completes before temperature becomes critical, demonstrating a 6.3x responsiveness gain, and a 6% energy efficiency improvement by racing to idle. We then analyze truncated sprints, wherein our software runtime system must intervene to prevent overheating by throttling parallelism and frequency before the computation is complete. To avoid oversubscription penalties (context switching inefficiencies after a truncated parallel sprint), we develop a sprint-aware task-based parallel runtime. We find that maximal-intensity sprinting is not always best, introduce the concept of sprint pacing, and evaluate an adaptive policy for selecting sprint intensity. We report initial results using a phase change heat sink to extend maximum sprint duration. Finally, we demonstrate that a sprint-and-rest operating regime can actually outperform thermally-limited sustained execution.","PeriodicalId":89892,"journal":{"name":"ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems","volume":"31 1","pages":"155-166"},"PeriodicalIF":0.0,"publicationDate":"2013-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83100793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 60

Wait-n-GoTM: improving HTM performance by serializing cyclic dependencies Wait-n-GoTM:通过序列化循环依赖来提高HTM性能

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2013-03-16 DOI: 10.1145/2451116.2451173

Syed Ali, Raza Jafri, G. Voskuilen, T. N. Vijaykumar

{"title":"Wait-n-GoTM: improving HTM performance by serializing cyclic dependencies","authors":"Syed Ali, Raza Jafri, G. Voskuilen, T. N. Vijaykumar","doi":"10.1145/2451116.2451173","DOIUrl":"https://doi.org/10.1145/2451116.2451173","url":null,"abstract":"Transactional memory (TM) has been proposed to alleviate some key programmability problems in chip multiprocessors. Most TMs optimistically allow concurrent transactions, detecting read-write or write-write conflicts. Upon conflicts, existing hardware TMs (HTMs) use one of three conflict-resolution policies: (1) always-abort, (2) always-wait for some conflicting transactions to complete, or (3) always-go past conflicts and resolve acyclic conflicts at commit or abort upon cyclic dependencies. While each policy has advantages, the policies degrade performance under contention by limiting concurrency (always-abort, always-wait) or incurring late aborts due to cyclic dependencies (always-go). Thus, while always-go avoids acyclic aborts, no policy avoids cyclic aborts. We propose Wait-n-GoTM (WnGTM) to increase concurrency while avoiding cyclic aborts. We observe that most cyclic dependencies are caused by threads interleaving multiple accesses to a few heavily-read-write-shared delinquent data cache blocks. These accesses occur in code sections called cycle inducer sections (CISTs). Accordingly, we propose Wait-n-Go (WnG) conflict-resolution to avoid many cyclic aborts by predicting and serializing the CISTs. To support the WnG policy, we extend previous HTMs to (1) allow multiple readers and writers, (2) scalably identify dependencies, and (3) detect cyclic dependencies via new mechanisms, namely, conflict transactional state, order-capture, and hardware timestamps, respectively. In 16-core simulations of STAMP, WnGTM achieves average speedups of 46% for higher-contention benchmarks and 28% for all benchmarks over always-abort (TokenTM) with low-contention benchmarks remaining unchanged, compared to always-go (DATM) and always-wait (LogTM-SE), which perform worse than and 6% better than TokenTM, respectively.","PeriodicalId":89892,"journal":{"name":"ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems","volume":"33 1","pages":"521-534"},"PeriodicalIF":0.0,"publicationDate":"2013-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80353867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 29

To hardware prefetch or not to prefetch?: a virtualized environment study and core binding approach 硬件预取还是不预取?虚拟化环境研究和核心绑定方法

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2013-03-16 DOI: 10.1145/2451116.2451155

Hui Kang, Jennifer L. Wong

{"title":"To hardware prefetch or not to prefetch?: a virtualized environment study and core binding approach","authors":"Hui Kang, Jennifer L. Wong","doi":"10.1145/2451116.2451155","DOIUrl":"https://doi.org/10.1145/2451116.2451155","url":null,"abstract":"Most hardware and software venders suggest disabling hardware prefetching in virtualized environments. They claim that prefetching is detrimental to application performance due to inaccurate prediction caused by workload diversity and VM interference on shared cache. However, no comprehensive or quantitative measurements to support this belief have been performed.\u0000 This paper is the first to systematically measure the influence of hardware prefetching in virtualized environments. We examine a wide variety of benchmarks on three types of chip-multiprocessors (CMPs) to analyze the hardware prefetching performance. We conduct extensive experiments by taking into account a number of important virtualization factors. We find that hardware prefetching has minimal destructive influence under most configurations. Only with certain application combinations does prefetching influence the overall performance.\u0000 To leverage these findings and make hardware prefetching effective across a diversity of virtualized environments, we propose a dynamic prefetching-aware VCPU-core binding approach (PAVCB), which includes two phases - classifying and binding. The workload of each VM is classified into different cache sharing constraint categories based upon its cache access characteristics, considering both prefetch requests and demand requests. Then following heuristic rules, the VCPUs of each VM are scheduled onto appropriate cores subject to cache sharing constraints. We show that the proposed approach can improve performance by 12% on average over the default scheduler and 46% over manual system administrator bindings across different workload combinations in the presence of hardware prefetching.","PeriodicalId":89892,"journal":{"name":"ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems","volume":"109 1","pages":"357-368"},"PeriodicalIF":0.0,"publicationDate":"2013-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83624002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 25

A study of the scalability of stop-the-world garbage collectors on multicores 停止世界垃圾收集器在多核上的可伸缩性研究

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2013-03-16 DOI: 10.1145/2451116.2451142

Lokesh Gidra, Gaël Thomas, Julien Sopena, M. Shapiro

引用次数: 63

Unikernels: library operating systems for the cloud Unikernels:面向云的库操作系统

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2013-03-16 DOI: 10.1145/2451116.2451167

Anil Madhavapeddy, R. Mortier, Charalampos Rotsos, Dave Scott, Balraj Singh, T. Gazagnaire, Steven Smith, S. Hand, J. Crowcroft

引用次数: 508

Research directions for 21st century computer systems: asplos 2013 panel 21世纪计算机系统研究方向:asplos 2013 panel

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2013-03-16 DOI: 10.1145/2451116.2451165

M. Hill

引用次数: 2

STABILIZER: statistically sound performance evaluation 稳定器:统计可靠的性能评价

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2013-03-16 DOI: 10.1145/2451116.2451141

Charlie Curtsinger, E. Berger

{"title":"STABILIZER: statistically sound performance evaluation","authors":"Charlie Curtsinger, E. Berger","doi":"10.1145/2451116.2451141","DOIUrl":"https://doi.org/10.1145/2451116.2451141","url":null,"abstract":"Researchers and software developers require effective performance evaluation. Researchers must evaluate optimizations or measure overhead. Software developers use automatic performance regression tests to discover when changes improve or degrade performance. The standard methodology is to compare execution times before and after applying changes.\u0000 Unfortunately, modern architectural features make this approach unsound. Statistically sound evaluation requires multiple samples to test whether one can or cannot (with high confidence) reject the null hypothesis that results are the same before and after. However, caches and branch predictors make performance dependent on machine-specific parameters and the exact layout of code, stack frames, and heap objects. A single binary constitutes just one sample from the space of program layouts, regardless of the number of runs. Since compiler optimizations and code changes also alter layout, it is currently impossible to distinguish the impact of an optimization from that of its layout effects.\u0000 This paper presents Stabilizer, a system that enables the use of the powerful statistical techniques required for sound performance evaluation on modern architectures. Stabilizer forces executions to sample the space of memory configurations by repeatedly re-randomizing layouts of code, stack, and heap objects at runtime. Stabilizer thus makes it possible to control for layout effects. Re-randomization also ensures that layout effects follow a Gaussian distribution, enabling the use of statistical tests like ANOVA. We demonstrate Stabilizer's efficiency (<7% median overhead) and its effectiveness by evaluating the impact of LLVM's optimizations on the SPEC CPU2006 benchmark suite. We find that, while -O2 has a significant impact relative to -O1, the performance impact of -O3 over -O2 optimizations is indistinguishable from random noise.","PeriodicalId":89892,"journal":{"name":"ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems","volume":"50 1","pages":"219-228"},"PeriodicalIF":0.0,"publicationDate":"2013-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86936568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 116

Transparent mutable replay for multicore debugging and patch validation 透明可变重放多核调试和补丁验证

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2013-03-16 DOI: 10.1145/2451116.2451130

N. Viennot, Siddharth Nair, Jason Nieh

{"title":"Transparent mutable replay for multicore debugging and patch validation","authors":"N. Viennot, Siddharth Nair, Jason Nieh","doi":"10.1145/2451116.2451130","DOIUrl":"https://doi.org/10.1145/2451116.2451130","url":null,"abstract":"We present Dora, a mutable record-replay system which allows a recorded execution of an application to be replayed with a modified version of the application. This feature, not available in previous record-replay systems, enables powerful new functionality. In particular, Dora can help reproduce, diagnose, and fix software bugs by replaying a version of a recorded application that is recompiled with debugging information, reconfigured to produce verbose log output, modified to include additional print statements, or patched to fix a bug.\u0000 Dora uses lightweight operating system mechanisms to record an application execution by capturing nondeterministic events to a log without imposing unnecessary timing and ordering constraints. It replays the log using a modified version of the application even in the presence of added, deleted, or modified operations that do not match events in the log. Dora searches for a replay that minimizes differences between the log and the replayed execution of the modified program. If there are no modifications, Dora provides deterministic replay of the unmodified program.\u0000 We have implemented a Linux prototype which provides transparent mutable replay without recompiling or relinking applications. We show that Dora is useful for reproducing, diagnosing, and fixing software bugs in real-world applications, including Apache and MySQL. Our results show that Dora (1) captures bugs and replays them with applications modified or reconfigured to produce additional debugging output for root cause diagnosis, (2) captures exploits and replays them with patched applications to validate that the patches successfully eliminate vulnerabilities, (3) records production workloads and replays them with patched applications to validate patches with realistic workloads, and (4) maintains low recording overhead on commodity multicore hardware, making it suitable for production systems.","PeriodicalId":89892,"journal":{"name":"ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems","volume":"56 1","pages":"127-138"},"PeriodicalIF":0.0,"publicationDate":"2013-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84897100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 44

Portable performance on heterogeneous architectures 异构架构上的可移植性能

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2013-03-16 DOI: 10.1145/2451116.2451162

P. Phothilimthana, Jason Ansel, Jonathan Ragan-Kelley, Saman P. Amarasinghe

{"title":"Portable performance on heterogeneous architectures","authors":"P. Phothilimthana, Jason Ansel, Jonathan Ragan-Kelley, Saman P. Amarasinghe","doi":"10.1145/2451116.2451162","DOIUrl":"https://doi.org/10.1145/2451116.2451162","url":null,"abstract":"Trends in both consumer and high performance computing are bringing not only more cores, but also increased heterogeneity among the computational resources within a single machine. In many machines, one of the greatest computational resources is now their graphics coprocessors (GPUs), not just their primary CPUs. But GPU programming and memory models differ dramatically from conventional CPUs, and the relative performance characteristics of the different processors vary widely between machines. Different processors within a system often perform best with different algorithms and memory usage patterns, and achieving the best overall performance may require mapping portions of programs across all types of resources in the machine.\u0000 To address the problem of efficiently programming machines with increasingly heterogeneous computational resources, we propose a programming model in which the best mapping of programs to processors and memories is determined empirically. Programs define choices in how their individual algorithms may work, and the compiler generates further choices in how they can map to CPU and GPU processors and memory systems. These choices are given to an empirical autotuning framework that allows the space of possible implementations to be searched at installation time. The rich choice space allows the autotuner to construct poly-algorithms that combine many different algorithmic techniques, using both the CPU and the GPU, to obtain better performance than any one technique alone. Experimental results show that algorithmic changes, and the varied use of both CPUs and GPUs, are necessary to obtain up to a 16.5x speedup over using a single program configuration for all architectures.","PeriodicalId":89892,"journal":{"name":"ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems","volume":"96 1","pages":"431-444"},"PeriodicalIF":0.0,"publicationDate":"2013-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75978137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 87