ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems最新文献_第5页

Power containers: an OS facility for fine-grained power and energy management on multicore servers 电源容器:用于在多核服务器上进行细粒度电源和能源管理的操作系统工具

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2013-03-16 DOI: 10.1145/2451116.2451124

Kai Shen, Arrvindh Shriraman, S. Dwarkadas, Xiao Zhang, Zhuan Chen

{"title":"Power containers: an OS facility for fine-grained power and energy management on multicore servers","authors":"Kai Shen, Arrvindh Shriraman, S. Dwarkadas, Xiao Zhang, Zhuan Chen","doi":"10.1145/2451116.2451124","DOIUrl":"https://doi.org/10.1145/2451116.2451124","url":null,"abstract":"Energy efficiency and power capping are critical concerns in server and cloud computing systems. They face growing challenges due to dynamic power variations from new client-directed web applications, as well as complex behaviors due to multicore resource sharing and hardware heterogeneity. This paper presents a new operating system facility called \"power containers\" that accounts for and controls the power and energy usage of individual fine-grained requests in multicore servers. This facility relies on three key techniques---1) online model that attributes multicore power (including shared maintenance power) to concurrently running tasks, 2) alignment of actual power measurements and model estimates to enable online model recalibration, and 3) on-the-fly application-transparent request tracking in multi-stage servers to isolate the power and energy contributions and customize per-request control. Our mechanisms enable new multicore server management capabilities including fair power capping that only penalizes power-hungry requests, and energy-aware request distribution between heterogeneous servers. Our evaluation uses three multicore processors (Intel Woodcrest, Westmere, and SandyBridge) and a variety of server and cloud computing (Google App Engine) workloads. Our results demonstrate the high accuracy of our request power accounting (no more than 11% errors) and the effectiveness of container-enabled power virus isolation and throttling. Our request distribution case study shows up to 25% energy saving compared to an alternative approach that recognizes machine heterogeneity but not fine-grained workload affinity.","PeriodicalId":89892,"journal":{"name":"ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems","volume":"33 1","pages":"65-76"},"PeriodicalIF":0.0,"publicationDate":"2013-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77670221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 106

Verifying systems rules using rule-directed symbolic execution 使用规则导向的符号执行验证系统规则

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2013-03-16 DOI: 10.1145/2451116.2451152

Heming Cui, Gang Hu, Jingyue Wu, Junfeng Yang

{"title":"Verifying systems rules using rule-directed symbolic execution","authors":"Heming Cui, Gang Hu, Jingyue Wu, Junfeng Yang","doi":"10.1145/2451116.2451152","DOIUrl":"https://doi.org/10.1145/2451116.2451152","url":null,"abstract":"Systems code must obey many rules, such as \"opened files must be closed.\" One approach to verifying rules is static analysis, but this technique cannot infer precise runtime effects of code, often emitting many false positives. An alternative is symbolic execution, a technique that verifies program paths over all inputs up to a bounded size. However, when applied to verify rules, existing symbolic execution systems often blindly explore many redundant program paths while missing relevant ones that may contain bugs.\u0000 Our key insight is that only a small portion of paths are relevant to rules, and the rest (majority) of paths are irrelevant and do not need to be verified. Based on this insight, we create WOODPECKER, a new symbolic execution system for effectively checking rules on systems programs. It provides a set of builtin checkers for common rules, and an interface for users to easily check new rules. It directs symbolic execution toward the program paths relevant to a checked rule, and soundly prunes redundant paths, exponentially speeding up symbolic execution. It is designed to be heuristic-agnostic, enabling users to leverage existing powerful search heuristics.\u0000 Evaluation on 136 systems programs totaling 545K lines of code, including some of the most widely used programs, shows that, with a time limit of typically just one hour for each verification run, WOODPECKER effectively verifies 28.7% of the program and rule combinations over bounded input, whereas an existing symbolic execution system KLEE verifies only 8.5%. For the remaining combinations, WOODPECKER verifies 4.6 times as many relevant paths as KLEE. With a longer time limit, WOODPECKER verifies much more paths than KLEE, e.g., 17 times as many with a fourhour limit. WOODPECKER detects 113 rule violations, including 10 serious data loss errors with 2 most serious ones already confirmed by the corresponding developers.","PeriodicalId":89892,"journal":{"name":"ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems","volume":"6 1","pages":"329-342"},"PeriodicalIF":0.0,"publicationDate":"2013-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80228299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 64

Volition: scalable and precise sequential consistency violation detection 意志:可扩展和精确的顺序一致性违规检测

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2013-03-16 DOI: 10.1145/2451116.2451174

Xuehai Qian, J. Torrellas, B. Sahelices, D. Qian

{"title":"Volition: scalable and precise sequential consistency violation detection","authors":"Xuehai Qian, J. Torrellas, B. Sahelices, D. Qian","doi":"10.1145/2451116.2451174","DOIUrl":"https://doi.org/10.1145/2451116.2451174","url":null,"abstract":"Sequential Consistency (SC) is the most intuitive memory model, and SC Violations (SCVs) produce unintuitive, typically incorrect executions. Most prior SCV detection schemes have used data races as proxies for SCVs, which is highly imprecise. Other schemes that have targeted data-race cycles are either too conservative or are designed only for two-processor cycles and snoopy-based systems.\u0000 This paper presents Volition, the first hardware scheme that detects SCVs in a relaxed-consistency machine precisely, in a scalable manner, and for an arbitrary number of processors in the cycle. Volition leverages cache coherence protocol transactions to dynamically detect cycles in memory-access orders across threads. When a cycle is about to occur, an exception is triggered. Volition can be used in both directory- and snoopy-based coherence protocols. Our simulations of Volition in a 64-processor multicore with directory-based coherence running SPLASH-2 and Parsec programs shows that Volition induces negligible traffic and execution overhead. In addition, it can detect SCVs with several processors. Volition is suitable for on-the-fly use.","PeriodicalId":89892,"journal":{"name":"ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems","volume":"24 1","pages":"535-548"},"PeriodicalIF":0.0,"publicationDate":"2013-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88622177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 27

Practical automatic loop specialization 实用自动回路专门化

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2013-03-16 DOI: 10.1145/2451116.2451161

Taewook Oh, Hanjun Kim, Nick P. Johnson, Jae W. Lee, David I. August

{"title":"Practical automatic loop specialization","authors":"Taewook Oh, Hanjun Kim, Nick P. Johnson, Jae W. Lee, David I. August","doi":"10.1145/2451116.2451161","DOIUrl":"https://doi.org/10.1145/2451116.2451161","url":null,"abstract":"Program specialization optimizes a program with respect to program invariants, including known, fixed inputs. These invariants can be used to enable optimizations that are otherwise unsound. In many applications, a program input induces predictable patterns of values across loop iterations, yet existing specializers cannot fully capitalize on this opportunity. To address this limitation, we present Invariant-induced Pattern based Loop Specialization (IPLS), the first fully-automatic specialization technique designed for everyday use on real applications. Using dynamic information-flow tracking, IPLS profiles the values of instructions that depend solely on invariants and recognizes repeating patterns across multiple iterations of hot loops. IPLS then specializes these loops, using those patterns to predict values across a large window of loop iterations. This enables aggressive optimization of the loop; conceptually, this optimization reconstructs recurring patterns induced by the input as concrete loops in the specialized binary. IPLS specializes real-world programs that prior techniques fail to specialize without requiring hints from the user. Experiments demonstrate a geomean speedup of 14.1% with a maximum speedup of 138% over the original codes when evaluated on three script interpreters and eleven scripts each.","PeriodicalId":89892,"journal":{"name":"ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems","volume":"119 1","pages":"419-430"},"PeriodicalIF":0.0,"publicationDate":"2013-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77370171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

Parallelizing data race detection 并行数据争用检测

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2013-03-16 DOI: 10.1145/2451116.2451120

Benjamin Wester, David Devecsery, Peter M. Chen, J. Flinn, S. Narayanasamy

{"title":"Parallelizing data race detection","authors":"Benjamin Wester, David Devecsery, Peter M. Chen, J. Flinn, S. Narayanasamy","doi":"10.1145/2451116.2451120","DOIUrl":"https://doi.org/10.1145/2451116.2451120","url":null,"abstract":"Detecting data races in multithreaded programs is a crucial part of debugging such programs, but traditional data race detectors are too slow to use routinely. This paper shows how to speed up race detection by spreading the work across multiple cores. Our strategy relies on uniparallelism, which executes time intervals of a program (called epochs) in parallel to provide scalability, but executes all threads from a single epoch on a single core to eliminate locking overhead. We use several techniques to make parallelization effective: dividing race detection into three phases, predicting a subset of the analysis state, eliminating sequential work via transitive reduction, and reducing the work needed to maintain multiple versions of analysis via factorization. We demonstrate our strategy by parallelizing a happens-before detector and a lockset-based detector. We find that uniparallelism can significantly speed up data race detection. With 4x the number of cores as the original application, our strategy speeds up the median execution time by 4.4x for a happens-before detector and 3.3x for a lockset race detector. Even on the same number of cores as the conventional detectors, the ability for uniparallelism to elide analysis locks allows it to reduce the median overhead by 13% for a happens-before detector and 8% for a lockset detector.","PeriodicalId":89892,"journal":{"name":"ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems","volume":"18 1","pages":"27-38"},"PeriodicalIF":0.0,"publicationDate":"2013-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74733695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 49

HOTL: a higher order theory of locality 一个高阶的局部性理论

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2013-03-16 DOI: 10.1145/2451116.2451153

Xiaoya Xiang, C. Ding, Hao Luo, Bin Bao

引用次数: 108

ConAir: featherweight concurrency bug recovery via single-threaded idempotent execution ConAir:通过单线程幂等执行恢复轻量级并发错误

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2013-03-16 DOI: 10.1145/2451116.2451129

Wei Zhang, M. Kruijf, Ang Li, Shan Lu, K. Sankaralingam

{"title":"ConAir: featherweight concurrency bug recovery via single-threaded idempotent execution","authors":"Wei Zhang, M. Kruijf, Ang Li, Shan Lu, K. Sankaralingam","doi":"10.1145/2451116.2451129","DOIUrl":"https://doi.org/10.1145/2451116.2451129","url":null,"abstract":"Many concurrency bugs are hidden in deployed software and cause severe failures for end-users. When they finally manifest and become known by developers, they are difficult to fix correctly. To support end-users, we need techniques that help software survive hidden concurrency bugs during production runs. To help developers, we need techniques that fix exposed concurrency bugs.\u0000 The state-of-the-art techniques on concurrency-bug fixing and survival only satisfy a subset of four important properties: compatibility, correctness, generality, and performance.We aim to develop a system that satisfies all of these four properties. To achieve this goal, we leverage two observations: (1) rolling back a single thread is sufficient to recover from most concurrency-bug failures; (2) reexecuting an idempotent region, which requires no memory-state checkpoint, is sufficient to recover from many concurrency-bug failures. Our system ConAir includes a static analysis component that automatically identifies potential failure sites, a static analysis component that automatically identifies the idempotent code regions around every failure site, and a code-transformation component that inserts rollback-recovery code around the identified idempotent regions.\u0000 We evaluated ConAir on 10 real-world concurrency bugs in widely used C/C++ open-source applications. These bugs cover different types of failure symptoms and root causes. Quantitatively, ConAir helps software survive failures caused by all of these bugs with negligible run-time overhead (<1%) and short recovery time. Qualitatively, ConAir can help recover from failures caused by unknown bugs. It guarantees that program semantics remain unchanged and requires no change to operating systems or hardware.","PeriodicalId":89892,"journal":{"name":"ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems","volume":"GE-19 1","pages":"113-126"},"PeriodicalIF":0.0,"publicationDate":"2013-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84608245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 40

Production-run software failure diagnosis via hardware performance counters 通过硬件性能计数器进行生产运行软件故障诊断

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2013-03-16 DOI: 10.1145/2451116.2451128

Joy Arulraj, Po-Chun Chang, Guoliang Jin, Shan Lu

{"title":"Production-run software failure diagnosis via hardware performance counters","authors":"Joy Arulraj, Po-Chun Chang, Guoliang Jin, Shan Lu","doi":"10.1145/2451116.2451128","DOIUrl":"https://doi.org/10.1145/2451116.2451128","url":null,"abstract":"Sequential and concurrency bugs are widespread in deployed software. They cause severe failures and huge financial loss during production runs. Tools that diagnose production-run failures with low overhead are needed. The state-of-the-art diagnosis techniques use software instrumentation to sample program properties at run time and use off-line statistical analysis to identify properties most correlated with failures. Although promising, these techniques suffer from high run-time overhead, which is sometimes over 100%, for concurrency-bug failure diagnosis and hence are not suitable for production-run usage.\u0000 We present PBI, a system that uses existing hardware performance counters to diagnose production-run failures caused by sequential and concurrency bugs with low overhead. PBI is designed based on several key observations. First, a few widely supported performance counter events can reflect a wide variety of common software bugs and can be monitored by hardware with almost no overhead. Second, the counter overflow interrupt supported by existing hardware and operating systems provides a natural and effective mechanism to conduct event sampling at user level. Third, the noise and non-determinism in interrupt delivery complements well with statistical processing.\u0000 We evaluate PBI using 13 real-world concurrency and sequential bugs from representative open-source server, client, and utility programs, and 10 bugs from a widely used software-testing benchmark. Quantitatively, PBI can effectively diagnose failures caused by these bugs with a small overhead that is never higher than 10%. Qualitatively, PBI does not require any change to software and presents a novel use of existing hardware performance counters.","PeriodicalId":89892,"journal":{"name":"ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems","volume":"17 1","pages":"101-112"},"PeriodicalIF":0.0,"publicationDate":"2013-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85984016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 37

Fine-grained fault tolerance using device checkpoints 使用设备检查点的细粒度容错

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2013-03-16 DOI: 10.1145/2451116.2451168

Asim Kadav, Matthew J. Renzelmann, M. Swift

{"title":"Fine-grained fault tolerance using device checkpoints","authors":"Asim Kadav, Matthew J. Renzelmann, M. Swift","doi":"10.1145/2451116.2451168","DOIUrl":"https://doi.org/10.1145/2451116.2451168","url":null,"abstract":"Recovering faults in drivers is difficult compared to other code because their state is spread across both memory and a device. Existing driver fault-tolerance mechanisms either restart the driver and discard its state, which can break applications, or require an extensive logging mechanism to replay requests and recreate driver state. Even logging may be insufficient, though, if the semantics of requests are ambiguous. In addition, these systems either require large subsystems that must be kept up-to-date as the kernel changes, or require substantial rewriting of drivers.\u0000 We present a new driver fault-tolerance mechanism that provides fine-grained control over the code protected. Fine-Grained Fault Tolerance (FGFT) isolates driver code at the granularity of a single entry point. It executes driver code as a transaction, allowing roll back if the driver fails. We develop a novel checkpointing mechanism to save and restore device state using existing power management code. Unlike past systems, FGFT can be incrementally deployed in a single driver without the need for a large kernel subsystem, but at the cost of small modifications to the driver.\u0000 In the evaluation, we show that FGFT can have almost zero runtime cost in many cases, and that checkpoint-based recovery can reduce the duration of a failure by 79% compared to restarting the driver. Finally, we show that applying FGFT to a driver requires little effort, and the majority of drivers in common classes already contain the power-management code needed for checkpoint/restore.","PeriodicalId":89892,"journal":{"name":"ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems","volume":"190 1","pages":"473-484"},"PeriodicalIF":0.0,"publicationDate":"2013-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79540802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 53

Improving GPGPU concurrency with elastic kernels 利用弹性内核提高GPGPU并发性

ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems Pub Date : 2013-03-16 DOI: 10.1145/2451116.2451160

Sreepathi Pai, M. J. Thazhuthaveetil, R. Govindarajan

{"title":"Improving GPGPU concurrency with elastic kernels","authors":"Sreepathi Pai, M. J. Thazhuthaveetil, R. Govindarajan","doi":"10.1145/2451116.2451160","DOIUrl":"https://doi.org/10.1145/2451116.2451160","url":null,"abstract":"Each new generation of GPUs vastly increases the resources available to GPGPU programs. GPU programming models (like CUDA) were designed to scale to use these resources. However, we find that CUDA programs actually do not scale to utilize all available resources, with over 30% of resources going unused on average for programs of the Parboil2 suite that we used in our work. Current GPUs therefore allow concurrent execution of kernels to improve utilization. In this work, we study concurrent execution of GPU kernels using multiprogram workloads on current NVIDIA Fermi GPUs. On two-program workloads from the Parboil2 benchmark suite we find concurrent execution is often no better than serialized execution. We identify that the lack of control over resource allocation to kernels is a major serialization bottleneck. We propose transformations that convert CUDA kernels into elastic kernels which permit fine-grained control over their resource usage. We then propose several elastic-kernel aware concurrency policies that offer significantly better performance and concurrency compared to the current CUDA policy. We evaluate our proposals on real hardware using multiprogrammed workloads constructed from benchmarks in the Parboil 2 suite. On average, our proposals increase system throughput (STP) by 1.21x and improve the average normalized turnaround time (ANTT) by 3.73x for two-program workloads when compared to the current CUDA concurrency implementation.","PeriodicalId":89892,"journal":{"name":"ASPLOS ... proceedings. International Conference on Architectural Support for Programming Languages and Operating Systems","volume":"7 1","pages":"407-418"},"PeriodicalIF":0.0,"publicationDate":"2013-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76269678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 218