Histoire & mesure最新文献_第3页

Hardware Threading Techniques for Multi-Threaded MPSoCs 多线程mpsoc的硬件线程技术

Histoire & mesure Pub Date : 2014-06-15 DOI: 10.1145/2613908.2613917

D. Watson, A. Ahmadinia, G. Morison, T. Buggy

引用次数: 1

Exploring Spiking Neural Network on Coarse-Grain Reconfigurable Architectures 基于粗粒度可重构结构的脉冲神经网络研究

Histoire & mesure Pub Date : 2014-06-15 DOI: 10.1145/2613908.2613916

Hassan Anwar, Syed M. A. H. Jafri, Sergei Dytckov, M. Daneshtalab, M. Ebrahimi, A. Hemani, J. Plosila, G. Beltrame, H. Tenhunen

引用次数: 4

Extending dataflow programs with throughput properties 扩展具有吞吐量属性的数据流程序

Histoire & mesure Pub Date : 2013-06-24 DOI: 10.1145/2489068.2489077

Manuel Selva, L. Morel, K. Marquet, S. Frénot

引用次数: 3

Directory based cache coherence verification logic in CMPs cache system CMPs缓存系统中基于目录的一致性验证逻辑

Histoire & mesure Pub Date : 2013-06-24 DOI: 10.1145/2489068.2489073

M. Dalui, K. Gupta, B. Sikdar

引用次数: 1

Performance analysis of multi-threaded multi-core CPUs 多线程多核cpu性能分析

Histoire & mesure Pub Date : 2013-06-24 DOI: 10.1145/2489068.2489076

Vijayalakshmi Saravanan, Kaushik S, S. Krishna, P. Iit, Guwahati India, D. Kothari

{"title":"Performance analysis of multi-threaded multi-core CPUs","authors":"Vijayalakshmi Saravanan, Kaushik S, S. Krishna, P. Iit, Guwahati India, D. Kothari","doi":"10.1145/2489068.2489076","DOIUrl":"https://doi.org/10.1145/2489068.2489076","url":null,"abstract":"Processors are constantly changing and becoming more advanced. They incorporate new concepts and ideas into the architecture with each evolution. One such concept is multi-threading. It aims at increasing the processors performance by reducing its idle time. It is the ability of the processor to execute multiple threads simultaneously on different cores present inside. Multi-threading concepts have also been incorporated in embedded systems which employ either a single-core or multi-core architecture. The aim of this study is to evaluate how effectively multi-threading improves processor utilization on multiple cores by taking both single and dual core processors and evaluating the performance of each by comparing the number of instructions executed per second. The results of this study give an edge to multi-threading in a single-core processor when compared to a dual-core processor when performance aspects are considered. Our analysis helps us to design the processor architecture in such a way that we utilize both the concepts of multi-threading and multi-core architecture to achieve maximum performance. The results of Simultaneous Multi-threading (SMT) performance improvement is encouraging when compared with dual-core processors.","PeriodicalId":84860,"journal":{"name":"Histoire & mesure","volume":"72 1","pages":"49-53"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84024058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Co-tuning of a hybrid electronic-optical network for reducing energy consumption in embedded CMPs 降低嵌入式cmp中能量消耗的混合电子光网络的共调谐

Histoire & mesure Pub Date : 2013-06-24 DOI: 10.1145/2489068.2489070

S. Bartolini, P. Grani

{"title":"Co-tuning of a hybrid electronic-optical network for reducing energy consumption in embedded CMPs","authors":"S. Bartolini, P. Grani","doi":"10.1145/2489068.2489070","DOIUrl":"https://doi.org/10.1145/2489068.2489070","url":null,"abstract":"Nanophotonic is a promising solution for on-chip interconnection due to its intrinsic low-latency and especially low-power features, desirable especially in future chip multiprocessors (CMPs) for rich client devices. In this paper we address the co-design of the parameters of a hybrid on-chip network featuring a traditional 2D mesh and a simple photonic helper ring aimed to improve performance and reduce energy consumption. As all the CMP traffic cannot be sustained in the considered simple optical interconnection without saturating the available bandwidth, and thus inducing performance and energy degradations, we identify the subset of coherency messages that are most worth to be accelerated through the low-energy optical path.\u0000 We investigate the management/arbitration strategies for the physically shared photonic path as they are crucial for reaching an effective exploitation of optical bandwidth according to their overhead and parallelism achieved in message transmission. Our results on multithreaded benchmarks, highlight that a careful selection of the most latency-critical messages to be routed on the photonic-path along with a Multiple-Writers-Single-Reader access scheme allows execution time and energy improvements up to 19% and 5%, respectively, for the 8-core setup and up to 16% and 13% for the 16-core configuration.\u0000 Furthermore, we show that the most aggressive ring access schemes allow the adoption of a four times slower electronic NoC that trades the achieved average speedup margin to obtain 70% overall energy savings, which is extremely important in energy constrained devices.","PeriodicalId":84860,"journal":{"name":"Histoire & mesure","volume":"10 1","pages":"9-16"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89316950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Proposing a new task model towards many-core architecture 提出了一种面向多核架构的任务模型

Histoire & mesure Pub Date : 2013-06-24 DOI: 10.1145/2489068.2489075

A. Shimada, Balazs Gerofi, A. Hori, Y. Ishikawa

引用次数: 6

Transparent and energy-efficient speculation on NUMA architectures for embedded MPSoCs 嵌入式mpsoc的NUMA架构的透明和节能推测

Histoire & mesure Pub Date : 2013-06-24 DOI: 10.1145/2489068.2489078

Dimitra Papagiannopoulou, R. I. Bahar, T. Moreshet, M. Herlihy, A. Marongiu, L. Benini

{"title":"Transparent and energy-efficient speculation on NUMA architectures for embedded MPSoCs","authors":"Dimitra Papagiannopoulou, R. I. Bahar, T. Moreshet, M. Herlihy, A. Marongiu, L. Benini","doi":"10.1145/2489068.2489078","DOIUrl":"https://doi.org/10.1145/2489068.2489078","url":null,"abstract":"High-end embedded systems such as smart phones, game consoles, GPS-enabled automotive systems, and home entertainment centers, are becoming ubiquitous. Like their general-purpose counterparts, and for many of the same energy-related reasons, embedded systems are turning to multicore architectures. Moreover, as the demand for more compute-intensive capabilities for embedded systems increases, these multicore architectures will evolve into many-core systems for improved performance or performance/area/Watt. These systems are often organized as cluster based Non-Uniform Memory Access (NUMA) architectures that provide the programmer with a shared-memory abstraction, with the cost of sharing memory (in terms of performance, energy, and complexity) varying substantially depending on the locations of the communicating processes. This paper investigates one of the principal challenges presented by these emerging NUMA architectures for embedded systems: providing efficient, energy-effective and convenient mechanisms for synchronization and communication. In this paper, we propose an initial solution based on hardware support for speculative synchronization.","PeriodicalId":84860,"journal":{"name":"Histoire & mesure","volume":"10 1","pages":"58-61"},"PeriodicalIF":0.0,"publicationDate":"2013-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90008809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A code generation method for system-level synthesis on ASIC, FPGA and manycore CGRA 基于ASIC、FPGA和多核CGRA的系统级综合代码生成方法

Histoire & mesure Pub Date : 2013-06-24 DOI: 10.1145/2489068.2489072

Shuo Li, Jamshaid Sarwar Malik, Shaoteng Liu, A. Hemani

引用次数: 4

Improving the programmability of STHORM-based heterogeneous systems with offload-enabled OpenMP 使用支持卸载的OpenMP改进基于sthorm的异构系统的可编程性

Histoire & mesure Pub Date : 2013-06-24 DOI: 10.1145/2489068.2489069

A. Marongiu, Alessandro Capotondi, Giuseppe Tagliavini, L. Benini

引用次数: 21