2014 International Conference on Field-Programmable Technology (FPT)最新文献_第3页

Doing FPGA in a former software company 在一家前软件公司做FPGA

2014 International Conference on Field-Programmable Technology (FPT) Pub Date : 2014-12-01 DOI: 10.1109/FPT.2014.7082744

Feng-Hsiung Hsu

引用次数: 0

Power supply noise aware evaluation framework for side channel attacks and countermeasures 侧信道攻击与对策的电源噪声感知评估框架

2014 International Conference on Field-Programmable Technology (FPT) Pub Date : 2014-12-01 DOI: 10.1109/FPT.2014.7082770

Jianlei Yang, Chenguang Wang, Yici Cai, Qiang Zhou

{"title":"Power supply noise aware evaluation framework for side channel attacks and countermeasures","authors":"Jianlei Yang, Chenguang Wang, Yici Cai, Qiang Zhou","doi":"10.1109/FPT.2014.7082770","DOIUrl":"https://doi.org/10.1109/FPT.2014.7082770","url":null,"abstract":"Side Channel Attack (SCA) aims to extract the secret information from cryptography chips by analyzing the leakage of physical parameters. Power analysis based SCA is a popular approach to obtain secret keys by monitoring the power consumption of cryptography chips. However, most SCA evaluation methods are performed on FPGA platforms while many parasitic physical effects cannot be revealed before the cryptography chips are taped out. Roughly ignoring these effects will significantly increase the attack difficulties due to the corresponding measurement noise. Power supply noise has been observed to be critical for power analysis based SCA. This paper demonstrates a power supply noise aware evaluation framework for practical side channel attack from cryptography system design to physical design. On-chip power delivery network is implemented among physical design stage. Consequently the supply noise of power network can be explored according to the post-layout implementation. Additionally, the countermeasures of cryptography chips could be enhanced by on-chip decapacitors placement due to its influences on the characteristics of power delivery network.","PeriodicalId":6877,"journal":{"name":"2014 International Conference on Field-Programmable Technology (FPT)","volume":"56 1","pages":"161-166"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87331421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Achieving higher performance of memcached by caching at network interface 通过网络接口缓存实现memcached的更高性能

2014 International Conference on Field-Programmable Technology (FPT) Pub Date : 2014-12-01 DOI: 10.1109/FPT.2014.7082799

E. Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, T. Asai, M. Motomura

引用次数: 1

Area efficient floating-point adder and multiplier with IEEE-754 compatible semantics 具有IEEE-754兼容语义的面积高效浮点加法器和乘法器

2014 International Conference on Field-Programmable Technology (FPT) Pub Date : 2014-12-01 DOI: 10.1109/FPT.2014.7082765

A. Ehliar

{"title":"Area efficient floating-point adder and multiplier with IEEE-754 compatible semantics","authors":"A. Ehliar","doi":"10.1109/FPT.2014.7082765","DOIUrl":"https://doi.org/10.1109/FPT.2014.7082765","url":null,"abstract":"In this paper we describe an open source floating-point adder and multiplier implemented using a 36-bit custom number format based on radix-16 and optimized for the 7-series FPGAs from Xilinx. Although this number format is not identical to the single-precision IEEE-754 format, the floatingpoint operators are designed in such a way that the numerical results for a given operation will be identical to the result from an IEEE-754 compliant operator with support for round-to-nearest even, NaNs and Infs, and subnormal numbers. The drawback of this number format is that the rounding step is more involved than in a regular, radix-2 based operator. On the other hand, the use of a high radix means that the area cost associated with normalization and denormalization can be reduced, leading to a net area advantage for the custom number format, under the assumption that support for subnormal numbers is required. The area of the floating-point adder in a Kintex-7 FPGA is 261 slice LUTs and the area of the floating-point multiplier is 235 slice LUTs and 2 DSP48E blocks. The adder can operate at 319 MHz and the multiplier can operate at a frequency of 305 MHz.","PeriodicalId":6877,"journal":{"name":"2014 International Conference on Field-Programmable Technology (FPT)","volume":"23 1","pages":"131-138"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78659877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 24

Parallel resampling for particle filters on FPGAs fpga上粒子滤波器的并行重采样

2014 International Conference on Field-Programmable Technology (FPT) Pub Date : 2014-12-01 DOI: 10.1109/FPT.2014.7082775

Shuanglong Liu, Grigorios Mingas, C. Bouganis

{"title":"Parallel resampling for particle filters on FPGAs","authors":"Shuanglong Liu, Grigorios Mingas, C. Bouganis","doi":"10.1109/FPT.2014.7082775","DOIUrl":"https://doi.org/10.1109/FPT.2014.7082775","url":null,"abstract":"Particle filters (PFs) are a set of algorithms that implement recursive Bayesian filtering, which represent the posterior distribution by a set of weighted samples. Resampling is a fundamental operation in PF algorithms. It consists of taking a population of samples and reconstructing it based on the weights attached to each sample, favouring the samples with large weights. However, resampling is computationally intensive when the number of samples is large and, most importantly, it is not inherently parallelizable like the other steps of the particle filter. Parallel computing devices such as Graphics Processing Units (GPUs) and Field Programmable Gate Arrays (FPGAs) have been proposed to accelerate resampling. In this paper, we propose novel parallel architectures that map four state-of-the-art resampling algorithms (systematic, residual systematic, Metropolis and Rejection resampling) to a FPGA. FPGA-specific optimisations are introduced to further optimize the performance of the above systems. The proposed architectures are implemented in a Virtex-6 LX240T FPGA device with half-utilization of logic resources. Compared to the respective state-of-the-art implementations on an NVIDIA K20 GPU, the achieved speedups are in the range of 1.7x-49x.","PeriodicalId":6877,"journal":{"name":"2014 International Conference on Field-Programmable Technology (FPT)","volume":"21 1","pages":"191-198"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74092905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21

An FPGA-based spectral anomaly detection system 基于fpga的光谱异常检测系统

2014 International Conference on Field-Programmable Technology (FPT) Pub Date : 2014-12-01 DOI: 10.1109/FPT.2014.7082772

Duncan J. M. Moss, Zhe Zhang, Nicholas J. Fraser, P. Leong

引用次数: 6

Analysis and optimization of a deeply pipelined FPGA soft processor 深度流水线FPGA软处理器的分析与优化

2014 International Conference on Field-Programmable Technology (FPT) Pub Date : 2014-12-01 DOI: 10.1109/FPT.2014.7082783

Hui Yan Cheah, Suhaib A. Fahmy, Nachiket Kapre

引用次数: 6

Assessing scrubbing techniques for Xilinx SRAM-based FPGAs in space applications 评估在空间应用中基于Xilinx sram的fpga的擦洗技术

2014 International Conference on Field-Programmable Technology (FPT) Pub Date : 2014-12-01 DOI: 10.1109/FPT.2014.7082803

Fredrik Brosser, Emil Milh, Vilhelm Geijer, P. Larsson-Edefors

引用次数: 27

Low-latency option pricing using systolic binomial trees 使用收缩二项树的低延迟期权定价

2014 International Conference on Field-Programmable Technology (FPT) Pub Date : 2014-12-01 DOI: 10.1109/FPT.2014.7082752

Aryan Tavakkoli, David B. Thomas

引用次数: 6

Fanout decomposition dataflow optimizations for FPGA-based Sparse LU factorization 基于fpga稀疏LU分解的扇出分解数据流优化

2014 International Conference on Field-Programmable Technology (FPT) Pub Date : 2014-12-01 DOI: 10.1109/FPT.2014.7082787

Siddhartha, Nachiket Kapre

引用次数: 2