2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS)最新文献_第7页

Machine-agnostic and Communication-aware Designs for MPI on Emerging Architectures 新兴体系结构上MPI的机器不可知和通信感知设计

2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS) Pub Date : 2020-05-01 DOI: 10.1109/IPDPS47924.2020.00014

J. Hashmi, Shulei Xu, B. Ramesh, Mohammadreza Bayatpour, H. Subramoni, D. Panda

{"title":"Machine-agnostic and Communication-aware Designs for MPI on Emerging Architectures","authors":"J. Hashmi, Shulei Xu, B. Ramesh, Mohammadreza Bayatpour, H. Subramoni, D. Panda","doi":"10.1109/IPDPS47924.2020.00014","DOIUrl":"https://doi.org/10.1109/IPDPS47924.2020.00014","url":null,"abstract":"Modern multi-/many-cores offer higher core-density, hardware multi-threading, deeper memory hierarchies, and diverse architectural capabilities. While emerging cloud-based HPC systems are able to deliver near-native performance, they bring more diversity to the architectures. The Message Passing Interface (MPI) offers the flexibility to arbitrarily bind application processes to CPU cores, however the static nature of these binding policies typically does not take applications’ communication patterns and underlying machine architecture into consideration. This lack of association between the dynamic nature of applications and architectural diversity offered by modern processors makes it difficult for the application developers and MPI designers to exploit modern multi-/many-core systems to their full potential. In this paper, we propose a set of low-level benchmarking based approaches and MPI-level designs to infer vendor-specific machine characteristics e.g., physical to virtual machine topologies, and dynamic communication patterns of the applications. By utilizing this information, we propose two novel algorithms to construct efficient MPI mappings for any given architecture and application communication pattern. The proposed designs are implemented in the MVAPICH2 MPI library and are evaluated on three different architectures using various micro-benchmarks and application kernels. We demonstrate up to 2X performance improvement for MPI collectives, and up to 3.5X and 26% improvement for NAS-CG and miniAMR application kernels, respectively.","PeriodicalId":6805,"journal":{"name":"2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS)","volume":"8 1","pages":"32-41"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84909438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

On the Complexity of Conditional DAG Scheduling in Multiprocessor Systems 多处理器系统中条件DAG调度的复杂性研究

2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS) Pub Date : 2020-05-01 DOI: 10.1109/IPDPS47924.2020.00112

A. Marchetti-Spaccamela, Nicole Megow, Jens Schlöter, M. Skutella, L. Stougie

{"title":"On the Complexity of Conditional DAG Scheduling in Multiprocessor Systems","authors":"A. Marchetti-Spaccamela, Nicole Megow, Jens Schlöter, M. Skutella, L. Stougie","doi":"10.1109/IPDPS47924.2020.00112","DOIUrl":"https://doi.org/10.1109/IPDPS47924.2020.00112","url":null,"abstract":"As parallel processing became ubiquitous in modern computing systems, parallel task models have been proposed to describe the structure of parallel applications. The workflow scheduling problem has been studied extensively over past years, focusing on multiprocessor systems and distributed environments (e.g. grids, clusters). In workflow scheduling, applications are modeled as directed acyclic graphs (DAGs). DAGs have also been introduced in the real-time scheduling community to model the execution of multi-threaded programs on a multi-core architecture. The DAG model assumes, in most cases, a fixed DAG structure capturing only straight-line code. Only recently, more general models have been proposed. In particular, the conditional DAG model allows the presence of control structures such as conditional (if-then-else) constructs. While first algorithmic results have been presented for the conditional DAG model, the complexity of schedulability analysis remains wide open. We perform a thorough analysis on the worst-case makespan (latest completion time) of a conditional DAG task under list scheduling (a.k.a. fixed-priority scheduling). We show several hardness results concerning the complexity of the optimization problem on multiple processors, even if the conditional DAG has a well-nested structure. For general conditional DAG tasks, the problem is intractable even on a single processor. Complementing these negative results, we show that certain practice-relevant DAG structures are very well tractable.","PeriodicalId":6805,"journal":{"name":"2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS)","volume":"25 1","pages":"1061-1070"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91093503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Transaction-Based Core Reliability 基于事务的核心可靠性

2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS) Pub Date : 2020-05-01 DOI: 10.1109/IPDPS47924.2020.00027

S. Do, M. Dubois

引用次数: 0

Engineering Worst-Case Inputs for Pairwise Merge Sort on GPUs gpu上成对归并排序的工程最坏情况输入

2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS) Pub Date : 2020-05-01 DOI: 10.1109/IPDPS47924.2020.00119

Kyle Berney, Nodari Sitchinava

{"title":"Engineering Worst-Case Inputs for Pairwise Merge Sort on GPUs","authors":"Kyle Berney, Nodari Sitchinava","doi":"10.1109/IPDPS47924.2020.00119","DOIUrl":"https://doi.org/10.1109/IPDPS47924.2020.00119","url":null,"abstract":"Currently, the fastest comparison-based sorting implementation on GPUs is implemented using a parallel pairwise merge sort algorithm (Thrust library). To achieve fast runtimes, the number of threads t to sort the input of N elements is fine-tuned experimentally for each generation of Nvidia GPUs in such a way that the number of elements E = N/t that each thread accesses in each merging round results in a small (empirically measured) number of shared memory contentions, known as bank conflicts, while balancing the number of global memory accesses and latency-hiding through thread oversubscription/occupancy.In this paper, we show that for every choice of E < w, such that E and w are co-prime, there exists an input permutation on which every warp of w threads of the Thrust merge sort is effectively reduced to using at most ⌈w/E⌉ threads due to sequentialization of shared memory accesses due to bank conflicts. Note that this matches the trivial worst-case bound on the loss of parallelism due to memory contentions for any warp accessing wE contiguous shared memory locations.Our proof is constructive, i.e., we are able to automatically construct such permutation for every value of E. We also show in practice that such constructed inputs result in up to ~50% slowdown, compared to the performance on random inputs, on modern GPU hardware.","PeriodicalId":6805,"journal":{"name":"2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS)","volume":"1 1","pages":"1133-1142"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79883104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Argus: Multi-Level Service Visibility Scoping for Internet-of-Things in Enterprise Environments Argus:企业环境中物联网的多层次服务可见性范围界定

2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS) Pub Date : 2020-05-01 DOI: 10.1109/IPDPS47924.2020.00073

Qian Zhou, Omkant Pandey, Fan Ye

{"title":"Argus: Multi-Level Service Visibility Scoping for Internet-of-Things in Enterprise Environments","authors":"Qian Zhou, Omkant Pandey, Fan Ye","doi":"10.1109/IPDPS47924.2020.00073","DOIUrl":"https://doi.org/10.1109/IPDPS47924.2020.00073","url":null,"abstract":"In IoT, what services from which nearby devices are available, must be discovered by a user’s device (e.g., smartphone) before she can issue commands to access them. Service visibility scoping in large scale, heterogeneous enterprise environments has multiple unique features, e.g., proximity based interactions, differentiated visibility according to device natures and user attributes, frequent user churns thus revocation. They render existing solutions completely insufficient. We propose Argus, a distributed algorithm offering three-level, fine-grained visibility scoping in parallel: i) Level 1 public visibility where services are identically visible to everyone; ii) Level 2 differentiated visibility where service visibility depends on users’ non-sensitive attributes; iii) Level 3 covert visibility where service visibility depends on users’ sensitive attributes that are never explicitly disclosed. Extensive analysis and experiments show that: i) Argus is secure; ii) its Level 2 is 10x as scalable and computationally efficient as work using Attribute-based Encryption, Level 3 is 10x as efficient as work using Paring-based Cryptography; iii) it is fast and agile for satisfactory user experience, costing 0.25 s to discover 20 Level 1 devices, and 0.63 s for Level 2 or Level 3 devices.","PeriodicalId":6805,"journal":{"name":"2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS)","volume":"66 1","pages":"654-663"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88985473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Solving the Container Explosion Problem for Distributed High Throughput Computing 解决分布式高吞吐量计算中的容器爆炸问题

2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS) Pub Date : 2020-05-01 DOI: 10.1109/IPDPS47924.2020.00048

Tim Shaffer, Nicholas L. Hazekamp, J. Blomer, D. Thain

引用次数: 4

Auto-tuning Parameter Choices in HPC Applications using Bayesian Optimization 使用贝叶斯优化的HPC应用程序中的自动调优参数选择

2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS) Pub Date : 2020-05-01 DOI: 10.1109/IPDPS47924.2020.00090

Harshitha Menon, A. Bhatele, T. Gamblin

{"title":"Auto-tuning Parameter Choices in HPC Applications using Bayesian Optimization","authors":"Harshitha Menon, A. Bhatele, T. Gamblin","doi":"10.1109/IPDPS47924.2020.00090","DOIUrl":"https://doi.org/10.1109/IPDPS47924.2020.00090","url":null,"abstract":"High performance computing applications, runtimes, and platforms are becoming more configurable to enable applications to obtain better performance. As a result, users are increasingly presented with a multitude of options to configure application-specific as well as platform-level parameters. The combined effect of different parameter choices on application performance is difficult to predict, and an exhaustive evaluation of this combinatorial parameter space is practically infeasible. One approach to parameter selection is a user-guided exploration of a part of the space. However, such an ad hoc exploration of the parameter space can result in suboptimal choices. Therefore, an automatic approach that can efficiently explore the parameter space is needed. In this paper, we propose HiPerBOt, a Bayesian optimization based configuration selection framework to identify application and platform-level parameters that result in high performing configurations. We demonstrate the effectiveness of HiPerBOt in tuning parameters that include compiler flags, runtime settings, and application-level options for several parallel codes, including, Kripke, Hypre, LULESH, and OpenAtom.","PeriodicalId":6805,"journal":{"name":"2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS)","volume":"34 1","pages":"831-840"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87196021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 26

EdgeIso: Effective Performance Isolation for Edge Devices EdgeIso:边缘设备的有效性能隔离

2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS) Pub Date : 2020-05-01 DOI: 10.1109/IPDPS47924.2020.00039

Yoonsung Nam, Yongjun Choi, Byeonghun Yoo, Hyeonsang Eom, Yongseok Son

{"title":"EdgeIso: Effective Performance Isolation for Edge Devices","authors":"Yoonsung Nam, Yongjun Choi, Byeonghun Yoo, Hyeonsang Eom, Yongseok Son","doi":"10.1109/IPDPS47924.2020.00039","DOIUrl":"https://doi.org/10.1109/IPDPS47924.2020.00039","url":null,"abstract":"Edges enable cloud services to be provided at low-latency and efficiently reduce the amount of transferred data by placing latency-critical tasks close to users. However, multi-tasking results in resource contention on edge devices, making it challenging to meet the service level objectives (SLOs) of tasks. Compared to the clouds, edges have relatively limited resources, but their tasks are required to meet a higher level of SLOs than clouds. Furthermore, modern edge devices equipped with additional accelerators (e.g., GPU) may worsen the resource contention due to the edge's integrated architecture, sharing the memory bandwidth between CPUs and accelerators. To address these challenges, we present EdgeIso, a light-weight scheduler that dynamically isolates the performance of tasks on edges. EdgeIso periodically monitors the resource contention and mitigates the contention to meet the SLOs of tasks by efficiently enforcing several isolation techniques (e.g., DVFS and core allocation) in an incremental manner. Moreover, it detects the changes of task executions or offered loads for tasks, thus handling high load fluctuations adaptively. We implement EdgeIso as a user-level scheduler on the Linux integrates into an NVIDIA Jetson TX2. Our experimental results show that EdgeIso improves the performance of the low-latency tasks significantly while improving resource efficiency compared with both the offloading and reservation scheme used in clouds.","PeriodicalId":6805,"journal":{"name":"2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS)","volume":"128 1","pages":"295-305"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85859047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Stitch It Up: Using Progressive Data Storage to Scale Science 缝合:使用渐进式数据存储来扩展科学

2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS) Pub Date : 2020-05-01 DOI: 10.1109/IPDPS47924.2020.00016

J. Lofstead, John Mitchell, Enze Chen

引用次数: 3

Coordinated Page Prefetch and Eviction for Memory Oversubscription Management in GPUs gpu内存超额订阅管理的协同页面预取与回收

2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS) Pub Date : 2020-05-01 DOI: 10.1109/IPDPS47924.2020.00056

Qi Yu, B. Childers, Libo Huang, Cheng Qian, Hui Guo, Zhiying Wang

{"title":"Coordinated Page Prefetch and Eviction for Memory Oversubscription Management in GPUs","authors":"Qi Yu, B. Childers, Libo Huang, Cheng Qian, Hui Guo, Zhiying Wang","doi":"10.1109/IPDPS47924.2020.00056","DOIUrl":"https://doi.org/10.1109/IPDPS47924.2020.00056","url":null,"abstract":"The adoption of unified memory and demand paging has simplified programming and eased memory management in discrete GPUs. However, long-latency page faults cause significant performance overhead. While several software-based mechanisms have been proposed to address this issue, they suffer from inefficiency when page prefetching and pre-eviction are combined. For example, a state-of-the-art page replacement policy, hierarchical page eviction (HPE), is inefficient when prefetching is enabled. Furthermore, the prefetcher semantics-aware pre-evicting policy, which pre-evicts continuous pages in bulk the way they were brought in by the prefetcher, may cause thrashing for some irregular applications.In this paper, coordinated page prefetch and eviction (CPPE) is proposed to manage memory oversubscription in GPUs with unified memory. CPPE incorporates a modified page eviction policy, MHPE, and an access pattern-aware prefetcher in a fine-grained manner: MHPE is aware of prefetch semantics and the prefetcher prefetches pages according to access patterns in eviction candidates selected by MHPE. Simulation results show that, when the GPU memory is 75% and 50% oversubscribed, CPPE achieves an average speedup of 1.56x and 1.64x (up to 10.97x) over the state-of-the-art baseline, which combines a sequential-local prefetcher and LRU pre-eviction policy. CPPE also outperforms other approaches, including Random/reserved LRU with the sequential-local prefetcher, and simply disabling prefetching under memory oversubscription.","PeriodicalId":6805,"journal":{"name":"2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS)","volume":"44 1","pages":"472-482"},"PeriodicalIF":0.0,"publicationDate":"2020-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88073110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11