Transaction-Based Core Reliability

Abstract

Modern microprocessor designs are becoming more vulnerable to transient faults leading to transient errors due to design trends mandating low supply voltage and reduced noise margins, shrinking feature sizes and increased transistor density for fast, low power circuits. Detecting and correcting transient errors in random logic in a processor core has become an important design goal and confronts design challenges such as input replication, error confinement and overheads minimization. Transactional Memory (TM) is a recent paradigm to improve the programmability and performance of parallel programs. TM has appeared in industry, providing hardware mechanisms for conflict detection and resolution, and checkpointing and rollback. In this paper, we leverage the features of Hardware TM (HTM) to provide processor cores with transient error detection and recovery at low hardware cost. We contribute to the current state of the art of dependable systems by proposing a novel microarchitecture.