2018 IEEE International Solid - State Circuits Conference - (ISSCC)最新文献_第9页

A reconfigurable 28/37GHz hybrid-beamforming MIMO receiver with inter-band carrier aggregation and RF-domain LMS weight adaptation 一种可重构的28/37GHz混合波束形成MIMO接收机，带间载波聚合和rf域LMS权重自适应

2018 IEEE International Solid - State Circuits Conference - (ISSCC) Pub Date : 2018-02-01 DOI: 10.1109/ISSCC.2018.8310189

Susnata Mondal, Rahul Singh, J. Paramesh

{"title":"A reconfigurable 28/37GHz hybrid-beamforming MIMO receiver with inter-band carrier aggregation and RF-domain LMS weight adaptation","authors":"Susnata Mondal, Rahul Singh, J. Paramesh","doi":"10.1109/ISSCC.2018.8310189","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310189","url":null,"abstract":"This paper presents a hybrid beamforming mm-wave MIMO receiver with two key innovations. First, it can be configured into three modes: two single-band multistream modes at 28 or 37 GHz that can support single-or multi-user MIMO, and a concurrent 28 and 37GHz dual-band single-stream phased-array inter-band carrier-aggregation mode. In all modes, the receiver features full connectivity from each antenna element input to each output stream, thereby maximizing usage of the available aperture. Second, the digitally programmable RF beamforming weights can be controlled by an external serial interface, or by an on-chip “one-port” mixed-signal adaptation loop that implements a technique that we call double-sampling time-multiplexed LMS (DS-TM-LMS). Unlike conventional LMS-type adaptation algorithms that require access to the individual array inputs and the combined output, and are therefore not easily amenable to a hybrid beamformer, DS-TM-LMS updates the RF-domain weights by accessing only the combined downconverted array outputs. Such adaptation is valuable for adaptive main-lobe, side-lobe or null steering, but more importantly, it can assist/augment codebook-based beam acquisition/tracking algorithms, which may fail in the presence of multipath, on- or off-channel interferers.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"46 1","pages":"72-74"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80348719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21

A 10Gb/s Si-photonic transceiver with 150μW 120μs-lock-time digitally supervised analog microring wavelength stabilization for 1Tb/s/mm2 Die-to-Die Optical Networks 用于1Tb/s/mm2模对模光网络的150μW、120μs锁时间数字监督模拟微环波长稳定的10Gb/s硅光子收发器

2018 IEEE International Solid - State Circuits Conference - (ISSCC) Pub Date : 2018-02-01 DOI: 10.1109/ISSCC.2018.8310328

Y. Thonnart, M. Zid, J. L. Jiménez, G. Waltener, R. Polster, O. Dubray, F. Lepin, S. Bernabé, S. Menezo, G. Pares, O. Castany, L. Boutafa, P. Grosse, B. Charbonnier, C. Baudot

{"title":"A 10Gb/s Si-photonic transceiver with 150μW 120μs-lock-time digitally supervised analog microring wavelength stabilization for 1Tb/s/mm2 Die-to-Die Optical Networks","authors":"Y. Thonnart, M. Zid, J. L. Jiménez, G. Waltener, R. Polster, O. Dubray, F. Lepin, S. Bernabé, S. Menezo, G. Pares, O. Castany, L. Boutafa, P. Grosse, B. Charbonnier, C. Baudot","doi":"10.1109/ISSCC.2018.8310328","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310328","url":null,"abstract":"Silicon photonics has allowed cost reduction and performance improvement for optical interconnects for the past few years, and short-reach wavelength-division-multiplexed (WDM) links have recently emerged thanks to the introduction of microring modulators and filters [1-5]. Nevertheless, the promise of optical networks-on-chip foreseen in [1] has to face the integration challenges of scalable low-footprint elementary drivers and robust operation under heavy thermal stress due to self-heating of the cores with varying loads. This work presents a 3D-stacked CMOS-on-Si-photonic transceiver chip, which includes base building-blocks targeting die-to-die WDM optical communication for multicore processors: 10Gbps 2.5Vpp OOK modulator driver, associated receiver, and digitally-supervised analog wavelength stabilization using microring heaters and remapping for 0-to-90°C operating range, for a total footprint of 0.01mm2 per microring.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"130 1","pages":"350-352"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75588071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20

A 20ns-write 45ns-read and 1014-cycle endurance memory module composed of 60nm crystalline oxide semiconductor transistors 一种由60nm晶体氧化物半导体晶体管组成的20ns写入45ns读取1014周期持久存储器模块

2018 IEEE International Solid - State Circuits Conference - (ISSCC) Pub Date : 2018-02-01 DOI: 10.1109/ISSCC.2018.8310395

Shuhei Maeda, S. Ohshita, K. Furutani, Y. Yakubo, T. Ishizu, T. Atsumi, Y. Ando, D. Matsubayashi, K. Kato, T. Okuda, M. Fujita, S. Yamazaki

引用次数: 5

A 1/2.8-inch 24Mpixel CMOS image sensor with 0.9μm unit pixels separated by full-depth deep-trench isolation 1/2.8英寸24Mpixel CMOS图像传感器，采用全深度深沟隔离技术分离0.9μm单位像素

2018 IEEE International Solid - State Circuits Conference - (ISSCC) Pub Date : 2018-02-01 DOI: 10.1109/ISSCC.2018.8310195

Yitae Kim, Wonchul Choi, D. Park, H. Jeoung, Bumsuk Kim, Youngsun Oh, Sung-Hun Oh, Byungjun Park, Euiyeol Kim, Yunki Lee, T. Jung, Yongwoong Kim, Sukki Yoon, Seokyong Hong, Jesuk Lee, Sangil Jung, Changrok Moon, Yongin Park, Duckhyung Lee, Duckhyun Chang

{"title":"A 1/2.8-inch 24Mpixel CMOS image sensor with 0.9μm unit pixels separated by full-depth deep-trench isolation","authors":"Yitae Kim, Wonchul Choi, D. Park, H. Jeoung, Bumsuk Kim, Youngsun Oh, Sung-Hun Oh, Byungjun Park, Euiyeol Kim, Yunki Lee, T. Jung, Yongwoong Kim, Sukki Yoon, Seokyong Hong, Jesuk Lee, Sangil Jung, Changrok Moon, Yongin Park, Duckhyung Lee, Duckhyun Chang","doi":"10.1109/ISSCC.2018.8310195","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310195","url":null,"abstract":"CMOS image sensors (CIS) have attracted much attention for the emerging mobile market, and the demand of high-resolution image sensors in mobile applications continues to increase [1-3]. For this reason, pixel pitch has been reduced down to 1.0μσι for mass production. Nevertheless, CISs are continuously scaling down to meet the strong demand for higher-resolution images. However, when the pixel size is reduced down to the sub-micron regime (possibly smaller than the diffraction limit), it is very important to consider photo sensitivity and crosstalk, which determine signal-to-noise ratio (SNR). To minimize degradation of photo sensitivity, back-side illumination (BSI), which collects light at the back side, is widely used instead of front-side illumination. In addition to BSI technology, deep-trench isolation (DTI) has emerged as a leading candidate to suppress crosstalk since it physically isolates the pixel. Previous work shows that partial-depth DTI can be applied in a 1.12μm-pitch pixel [4]. Furthermore, full-depth DTI has been demonstrated in a 1.12μm pixel with 24% larger full-well capacity (FWC), 30% smaller YSNR10, 2.0dB higher SNR, and especially for lower crosstalk (12.5%) compared with a conventional one [5]. In this work, a 24-Mpixel CIS with 0.9μσι unit pixels that takes advantage of full-depth DTI is demonstrated.","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"7 1","pages":"84-86"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76987117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

A high-efficiency 28GHz outphasing PA with 23dBm output power using a triaxial balun combiner 采用三轴平衡合成器，输出功率为23dBm的高效28GHz分相PA

2018 IEEE International Solid - State Circuits Conference - (ISSCC) Pub Date : 2018-02-01 DOI: 10.1109/ISSCC.2018.8310240

Bagher Rabet, J. Buckwalter

引用次数: 32

A 64Gb/s PAM-4 transceiver utilizing an adaptive threshold ADC in 16nm FinFET 采用16nm FinFET自适应阈值ADC的64Gb/s PAM-4收发器

2018 IEEE International Solid - State Circuits Conference - (ISSCC) Pub Date : 2018-02-01 DOI: 10.1109/ISSCC.2018.8310208

Luke Wang, Yingying Fu, Marc-Andre LaCroix, Euhan Chong, A. C. Carusone

{"title":"A 64Gb/s PAM-4 transceiver utilizing an adaptive threshold ADC in 16nm FinFET","authors":"Luke Wang, Yingying Fu, Marc-Andre LaCroix, Euhan Chong, A. C. Carusone","doi":"10.1109/ISSCC.2018.8310208","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310208","url":null,"abstract":"ADC-based transceivers having up to 8 bits of resolution have been reported for PAM-4 links above 50Gb/s [1,2], although fewer bits are sufficient and offer lower power for short reach (SR) channels. To further reduce the power consumption of ADC-based wireline transceivers, non-uniform quantization has been explored [3,4] using performance metrics for the complete link, such as bit-error rate (BER), to optimize the quantizer thresholds. Both [3,4] are PAM-2 (NRZ) receivers, demonstrating non-uniform quantization specifically for a decision feedback equalizer (DFE) at 10Gb/s and a feedforward equalizer (FFE) at 4Gb/s respectively. An LMS algorithm in [4] adjusts the threshold levels requiring fine-tuning (8b resolution). This paper presents a 64Gb/s PAM-4 transceiver utilizing an ADC-based receiver (RX), with an analog front-end (AFE) based on a 6b, 1b folding, flash ADC with adaptive threshold levels. A fast greedy-search algorithm is used to choose the optimal quantizer thresholds for minimum BER over a given channel. This provides a near-optimal way of power-scaling the ADC when the channel loss doesn't require the ADC's full resolution. The optimization can work in the background for any equalizer structure, does not place additional requirements on the ADC design, and never diverges, unlike LMS-based approaches [4].","PeriodicalId":6617,"journal":{"name":"2018 IEEE International Solid - State Circuits Conference - (ISSCC)","volume":"45 1","pages":"110-112"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84822146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21

A 27.8Gb/s 11.5pJ/b 60GHz transceiver in 28nm CMOS with polarization MIMO 一个27.8Gb/s 11.5pJ/b 60GHz的28nm CMOS偏振MIMO收发器

2018 IEEE International Solid - State Circuits Conference - (ISSCC) Pub Date : 2018-02-01 DOI: 10.1109/ISSCC.2018.8310236

S. Daneshgar, K. Dasgupta, C. Thakkar, A. Chakrabarti, Shuhei Yamada, D. Choudhury, J. Jaussi, B. Casper

引用次数: 29

F4: Circuit and system techniques for mm-wave multi-antenna systems F4:毫米波多天线系统的电路和系统技术

2018 IEEE International Solid - State Circuits Conference - (ISSCC) Pub Date : 2018-02-01 DOI: 10.1109/ISSCC.2018.8310406

P. Busson, H. Luong, C. Hung, H. Krishnaswamy, T. Georgantas, P. Mercier

引用次数: 1

An 8-channel 13GHz ESR-on-a-Chip injection-locked vco-array achieving 200μM-concentration sensitivity 8通道13GHz esr片上注入锁定vco阵列，浓度灵敏度达到200μ m

2018 IEEE International Solid - State Circuits Conference - (ISSCC) Pub Date : 2018-02-01 DOI: 10.1109/ISSCC.2018.8310330

Anh Chu, Benedikt Schlecker, K. Lips, M. Ortmanns, J. Anders

引用次数: 20

A continuous-mode harmonically tuned 19-to-29.5GHz ultra-linear PA supporting 18Gb/s at 18.4% modulation PAE and 43.5% peak PAE 一种连续模式谐波调谐19- 29.5 ghz超线性放大器，在18.4%调制PAE和43.5%峰值PAE下支持18Gb/s

2018 IEEE International Solid - State Circuits Conference - (ISSCC) Pub Date : 2018-02-01 DOI: 10.1109/ISSCC.2018.8310358

Tso-Wei Li, Min-Yu Huang, Hua Wang

引用次数: 48