2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT)最新文献_第5页

Fuzzy based Fault Tolerant shunt Active Power Filter 基于模糊容错的并联有源电力滤波器

2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT) Pub Date : 2014-07-10 DOI: 10.1109/ICCICCT.2014.6993169

N. Madhuri, S. Doradla, M. Kalavathi

引用次数: 4

Adaptive thresholding: A comparative study 自适应阈值法的比较研究

2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT) Pub Date : 2014-07-10 DOI: 10.1109/ICCICCT.2014.6993140

Payel Roy, Goutami Dey, S. Dutta, Sayan Chakraborty, N. Dey, R. Ray

引用次数: 94

Android malware attacks and countermeasures: Current and future directions Android恶意软件攻击和对策:当前和未来的方向

2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT) Pub Date : 2014-07-10 DOI: 10.1109/ICCICCT.2014.6992944

Rahul Raveendranath, V. Rajamani, Anoop Babu, S. K. Datta

引用次数: 33

Segmentation in Malayalam OCR — Handling broken characters using active contour model 马来语OCR中的分割-使用活动轮廓模型处理破碎字符

2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT) Pub Date : 2014-07-10 DOI: 10.1109/ICCICCT.2014.6993097

M. Praseetha, S. Deepa

引用次数: 0

Cloud storage system enabling secure privacy preserving third party audit 云存储系统支持安全隐私保护第三方审计

2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT) Pub Date : 2014-07-10 DOI: 10.1109/ICCICCT.2014.6993049

D. Rewadkar, Suchita Y. Ghatage

{"title":"Cloud storage system enabling secure privacy preserving third party audit","authors":"D. Rewadkar, Suchita Y. Ghatage","doi":"10.1109/ICCICCT.2014.6993049","DOIUrl":"https://doi.org/10.1109/ICCICCT.2014.6993049","url":null,"abstract":"Cloud computing is a revolutionary new approach to how computing services are produced and consumed. It is an abstraction of the concept of pooling resources and presenting them as virtual resources. Using cloud computing resources, data, computations, and services can be shared over scalable network of nodes; these nodes may represent the datacenters, end user computers and web services. On the same note cloud storage refers to storing the data on a remote storage located at other organization's infrastructure. The data storage is maintained and managed by the organization; the user will pay for the storage space which is used. Outsourcing data ultimately relinquishes the control of data from user and the fate of data is in control of the cloud server. As the data is stored on cloud server, the storage correctness of data is put on risk. The cloud server is managed by cloud service provider which is a different administrative entity, so ensuring the data integrity is of prime importance. This article studies the problems of ensuring data storage correctness and proposes an efficient and secure method to address these issues. A third party auditor is introduced securely, who will on behalf of users request will periodically verify the data integrity of the data stored on cloud server. There will not be any online burden on user and security of data will be maintained as the data will not be shared directly with the third party auditor. A homomorphic encryption scheme is used to encrypt the data which will be shared with the TPA. The results can be further extended to enable the third party auditor to do multiple auditing.","PeriodicalId":6615,"journal":{"name":"2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT)","volume":"52 1","pages":"695-699"},"PeriodicalIF":0.0,"publicationDate":"2014-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79127852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Smile detection from still images using KNN algorithm 基于KNN算法的静态图像微笑检测

2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT) Pub Date : 2014-07-10 DOI: 10.1109/ICCICCT.2014.6993006

T. George, Sumi P. Potty, Sneha Jose

引用次数: 18

Area efficient fully parallel distributed arithmetic architecture for one-dimensional discrete cosine transform 一维离散余弦变换的面积高效全并行分布式算法结构

2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT) Pub Date : 2014-07-10 DOI: 10.1109/ICCICCT.2014.6992973

Teena Susan Elias, P. Dhanusha

{"title":"Area efficient fully parallel distributed arithmetic architecture for one-dimensional discrete cosine transform","authors":"Teena Susan Elias, P. Dhanusha","doi":"10.1109/ICCICCT.2014.6992973","DOIUrl":"https://doi.org/10.1109/ICCICCT.2014.6992973","url":null,"abstract":"The paper describes the design of one-dimensional discrete cosine transform (DCT) which is widely used in image and video compression systems. The objective of this paper is to design an area efficient fully parallel distributed arithmetic (DA) architecture for one-dimensional DCT to be implemented on field programmable gate array (FPGA). DCT requires large amount of mathematical computations including multiplications and accumulations. The multipliers consume increased power and area; hence multipliers are completely discarded in the proposed design. Distributed arithmetic is a method of modification at bit stream for sum of product or vector dot product to hide the multiplications. DA is very much suitable for FPGA designs as it reduces the size of a multiply and accumulate hardware. The speed is increased in the proposed design with the fully parallel approach. In this work, existing DA architecture for 1D-DCT and the proposed area efficient fully parallel DA architecture for 1D-DCT are realized. The simulation is performed using Modelsim6.2b and synthesized with Xilinx IS E Simulator. The 1D-DCT can be extended to 2D-DCT by using row column decomposition technique.","PeriodicalId":6615,"journal":{"name":"2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT)","volume":"29 1","pages":"294-299"},"PeriodicalIF":0.0,"publicationDate":"2014-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90665341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

An approach to design a matrix inversion hardware module using FPGA 一种基于FPGA的矩阵反演硬件模块设计方法

2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT) Pub Date : 2014-07-10 DOI: 10.1109/ICCICCT.2014.6992935

G. V. A. Kumar, T. Subbareddy, Bommepalli Madhava Reddy, N. Raju, V. Elamaran

{"title":"An approach to design a matrix inversion hardware module using FPGA","authors":"G. V. A. Kumar, T. Subbareddy, Bommepalli Madhava Reddy, N. Raju, V. Elamaran","doi":"10.1109/ICCICCT.2014.6992935","DOIUrl":"https://doi.org/10.1109/ICCICCT.2014.6992935","url":null,"abstract":"This study work is basically aimed at designing and testing of hardware module to perform inversion operation of a matrix in a small time. Here, an approach is made for calculating 3×3 matrix inverse. There are many mathematical methods available for performing matrix inversion and out of them a suitable method, like Adjoint Matrix Method is selected by analysing the computational requirements. The mathematical method of calculating the inverse of matrix is then suitably converted into VHDL code. The code is then tested for simulation using a set of test matrices. After simulation is verified by checking the results of test inputs the code is tested for synthesizability. After the synthesizability is verified then it is finally tested for hardware verification by dumping into FPGA. Altera's DE1 board which consists a Cyclone-II series FPGA EP2C20F484C7 FPGA is used for this study. The test inputs can be fed in either by using on board GPIO or UI or S RAM. The outputs are taken the same way either by GPIO or UI or written to S RAM and are then to be verified by comparing with actual results.","PeriodicalId":6615,"journal":{"name":"2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT)","volume":"91 1","pages":"87-90"},"PeriodicalIF":0.0,"publicationDate":"2014-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85874536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Improved transmission control protocol model 改进的传输控制协议模型

2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT) Pub Date : 2014-07-10 DOI: 10.1109/ICCICCT.2014.6992948

A. Parashar

引用次数: 1

FPGA synthesis of area efficient data path for reconfigurable FIR filter 可重构FIR滤波器区域高效数据路径的FPGA合成

2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT) Pub Date : 2014-07-10 DOI: 10.1109/ICCICCT.2014.6992985

R. Saranya, C. Pradeep

{"title":"FPGA synthesis of area efficient data path for reconfigurable FIR filter","authors":"R. Saranya, C. Pradeep","doi":"10.1109/ICCICCT.2014.6992985","DOIUrl":"https://doi.org/10.1109/ICCICCT.2014.6992985","url":null,"abstract":"Reconfigurable computing for DSP remains an active area of research as the need for integration with more traditional DSP technologies become apparent. Traditionally, most of the work in the field of reconfigurable computing was focused on fine-grained FPGA devices. Over the years, the focus was shifted from bit level granularity to a more coarse grained composition. In this paper, we present the synthesis of high-throughput and area efficient data path for reconfigurable Finite Impulse Response (FIR) filter. FIR filters have been and continue to be important building blocks in many DSP systems. It computes the output by multiplying a set of input samples with a set of coefficients followed by addition. Here, the multiplication and addition processess are based on the concept of Divide and Conquer approach. Separate multiplier and adder blocks are designed to model the FIR filter. The design was modeled using Verilog HDL and simulated and synthesized using Xilinx IS E 14.2. The design was also synthesized in Leonardo Spectrum. A comparison was made by implementing the design on different FPGA devices. The result shows that the proposed system has better device utilization in Virtex-5 FPGA.","PeriodicalId":6615,"journal":{"name":"2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT)","volume":"11 1","pages":"349-354"},"PeriodicalIF":0.0,"publicationDate":"2014-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81668400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1