2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)最新文献

Side channel modeling attacks on 65nm arbiter PUFs exploiting CMOS device noise 利用CMOS器件噪声的65nm仲裁puf侧通道建模攻击

2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) Pub Date : 2013-06-02 DOI: 10.1109/HST.2013.6581579

Jeroen Delvaux, I. Verbauwhede

引用次数: 160

Stability analysis of a physical unclonable function based on metal resistance variations 基于金属电阻变化的物理不可克隆函数的稳定性分析

2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) Pub Date : 2013-06-02 DOI: 10.1109/HST.2013.6581580

J. Ju, R. Chakraborty, Charles Lamech, J. Plusquellic

引用次数: 21

Low-cost and area-efficient FPGA implementations of lattice-based cryptography 基于格的加密的低成本和面积高效的FPGA实现

2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) Pub Date : 2013-06-02 DOI: 10.1109/HST.2013.6581570

Aydin Aysu, C. Patterson, P. Schaumont

引用次数: 85

A bulk built-in sensor for detection of fault attacks 用于检测故障攻击的大块内置传感器

2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) Pub Date : 2013-06-02 DOI: 10.1109/HST.2013.6581565

R. P. Bastos, F. Sill, J. Dutertre, M. Flottes, G. D. Natale, B. Rouzeyre

引用次数: 20

On hardware Trojan design and implementation at register-transfer level 寄存器传输级硬件木马的设计与实现

2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) Pub Date : 2013-06-02 DOI: 10.1109/HST.2013.6581574

Jie Zhang, Q. Xu

{"title":"On hardware Trojan design and implementation at register-transfer level","authors":"Jie Zhang, Q. Xu","doi":"10.1109/HST.2013.6581574","DOIUrl":"https://doi.org/10.1109/HST.2013.6581574","url":null,"abstract":"There have been a number of hardware Trojan (HT) designs at register-transfer level (RTL) in the literature, which mainly describe their malicious behaviors and trigger mechanisms. Generally speaking, the stealthiness of the HTs is shown with extremely low sensitization probability of the trigger events. In practice, however, based on the fact that HTs are not sensitized with verification test cases (otherwise their malicious behaviors would have manifested themselves), designers could focus on verification corners for HT detection. Consequently, a stealthy HT not only requires to be hard to trigger, but also needs to be able to evade those hardware trust verification techniques based on “unused circuit identification (UCI)”. In this paper, we present new HT design and implementation techniques that are able to achieve the above objectives. In addition, attackers would like to be able to control their HTs easily, which is also considered in the proposed HT design methodology. Experimental results demonstrate that HTs constructed with the proposed technique are both hard to be detected and easy to be controlled when compared to existing HTs shown in the literature.","PeriodicalId":6337,"journal":{"name":"2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"13 1","pages":"107-112"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90059339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 46

Structural transformation for best-possible obfuscation of sequential circuits 结构转换的最佳可能混淆顺序电路

2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) Pub Date : 2013-06-02 DOI: 10.1109/HST.2013.6581566

Li Li, H. Zhou

引用次数: 43

Malicious circuitry detection using fast timing characterization via test points 恶意电路检测使用快速时序表征通过测试点

2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) Pub Date : 2013-06-02 DOI: 10.1109/HST.2013.6581575

Sheng Wei, M. Potkonjak

引用次数: 12

On-chip lightweight implementation of reduced NIST randomness test suite 片上轻量级实现减少NIST随机测试套件

2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) Pub Date : 2013-06-02 DOI: 10.1109/HST.2013.6581572

Vikram B. Suresh, D. Antonioli, W. Burleson

{"title":"On-chip lightweight implementation of reduced NIST randomness test suite","authors":"Vikram B. Suresh, D. Antonioli, W. Burleson","doi":"10.1109/HST.2013.6581572","DOIUrl":"https://doi.org/10.1109/HST.2013.6581572","url":null,"abstract":"On-chip Random Number Generators (RNGs) are critical components in lightweight ubiquitous devices like RFIDs and smart cards. These devices require low cost test methodologies and security against cryptanalytic and invasive attacks. In this work we propose an on-chip implementation of a reduced set of NIST-SP-800-22 randomness test suite to provide on-line RNG testing for low cost security devices along with runtime monitoring of RNG performance. The on-chip NIST module monitors the effect of dynamic variation of operating condition and time dependent wear-out on RNG circuits. It indicates invasive attacks on RNG and allows the secure system to take protective measures. Six NIST tests are optimized to a hardware design friendly format, but in compliance with the NIST standard. The lightweight implementations reduce complex statistical and arithmetic operations of conventional NIST tests to a series of bit stream count and compare operations. A cycle-to-cycle serial test of incoming bits from RNG eliminates need for additional storage. A partial re-configurable feature is designed to set the pass/fail threshold for each test depending on the system requirements. The on-chip NIST module, although not exhaustive, is an effective layer of validation and security for RNG circuits. The six 128-bit tests implemented in 45nm NCSU PDK have a total synthesized area of ~1926.sq.um for an optimized frequency of 2GHz. The total dynamic power is 3.75mW and leakage power is 10.5μW. At 2Gbps, the NIST module consumes 1.87pJ/bit. The lightweight ultra-low power implementation is scalable for larger input bit samples.","PeriodicalId":6337,"journal":{"name":"2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"23 1","pages":"93-98"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80500306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21

Localized electromagnetic analysis of RO PUFs RO puf的局域电磁分析

2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) Pub Date : 2013-06-02 DOI: 10.1109/HST.2013.6581559

D. Merli, Johann Heyszl, Benedikt Heinz, Dieter Schuster, F. Stumpf, G. Sigl

引用次数: 68

Novel strong PUF based on nonlinearity of MOSFET subthreshold operation 基于MOSFET亚阈值工作非线性的新型强PUF

2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) Pub Date : 2013-06-02 DOI: 10.1109/HST.2013.6581558

Mukund Kalyanaraman, M. Orshansky

{"title":"Novel strong PUF based on nonlinearity of MOSFET subthreshold operation","authors":"Mukund Kalyanaraman, M. Orshansky","doi":"10.1109/HST.2013.6581558","DOIUrl":"https://doi.org/10.1109/HST.2013.6581558","url":null,"abstract":"Many strong silicon physical unclonable functions (PUFs) are known to be vulnerable to machine-learning attacks due to linear separability of the output function. This significantly limits their potential as reliable security primitives. We introduce a novel strong silicon PUF based on the exponential current-voltage behavior in subthreshold region of FET operation which injects strong nonlinearity into the response of the PUF. The PUF, which we term subthreshold current array (SCA) PUF, is implemented as a pair of two-dimensional n × k transistor arrays with all devices subject to stochastic variability operating in subthreshold region. Our PUF is fundamentally different from earlier attempts to inject nonlinearity via digital control techniques, which could also be used with SCA-PUF. Voltages produced by nominally identical arrays are compared to produce a random binary response. SCA-PUF shows excellent security properties. The average inter-class Hamming distance, a measure of uniqueness, is 50.2%. The average intra-class Hamming distance, a measure of response stability, is 4.17%. Crucially, we demonstrate that the introduced PUF is much less vulnerable to modeling attacks. Using machine-learning techniques of support-vector machine with radial basis function kernel and logistic regression for best nonlinear learnability, we observe that “information leakage” (rate of error reduction with learning) is much lower than for delay-based PUFs. Over a wide range of the number of observed challenge-response pairs, the error rate is 3-35X higher than for the delay-based PUF. We also demonstrate an enhanced SCAPUF design utilizing XOR scrambling and show that it has an up to 30X higher error rate compared to the XOR delay-based PUF.","PeriodicalId":6337,"journal":{"name":"2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"27 1","pages":"13-18"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89370464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 53