Mingzhe Wu, Jun Hao, Jiazhe Li, Qi Zhang, Yanyong Yang, Kehu Yang
{"title":"Optimised Operations and Modulation Scheme for Simplified Seven-Level Hybrid-Clamped Converters","authors":"Mingzhe Wu, Jun Hao, Jiazhe Li, Qi Zhang, Yanyong Yang, Kehu Yang","doi":"10.1049/pel2.70028","DOIUrl":"https://doi.org/10.1049/pel2.70028","url":null,"abstract":"<p>Seven-level hybrid-clamped (7L-HC) converters are new and promising candidates for high-power medium-voltage applications. Their configurations can be simplified further by reducing one of the two flying capacitors per phase. However, such simplification significantly reduces the available redundant states, making it hard for dc-link capacitors balancing and operation optimisation. In this article, the optimised operations and a low switching frequency modulation scheme are proposed for S7L-HC converters. Various new switching states are explored to help reduce the switching frequency, facilitate the balance of switching frequency distributions and reduction of the dynamic voltage stress on switches. The proposed modulation based on an improved selective harmonic elimination pulse width modulation (PWM) can achieve voltage balancing for all capacitors under a low switching frequency. Simulation and experimental results verify the proposed operations and modulation scheme.</p>","PeriodicalId":56302,"journal":{"name":"IET Power Electronics","volume":"18 1","pages":""},"PeriodicalIF":1.7,"publicationDate":"2025-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/pel2.70028","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143749320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Transient Current Sharing Method for Parallel SiC MOSFETs Based on Gate-Source Voltage Difference","authors":"Hao Pan, Haichuan Zhou, Zhen Wang, Yufeng Zhao, Limin Jia","doi":"10.1049/pel2.70030","DOIUrl":"https://doi.org/10.1049/pel2.70030","url":null,"abstract":"<p>In the design of high-power converters, significant parameter dispersion among different SiC MOSFET devices can cause substantial current differences during switching when devices are directly paralleled. To address this issue, a method is proposed to suppress transient current imbalance based on gate-source voltage compensation. First, the impact mechanism of threshold voltage differences on transient current imbalance during the switching of parallel SiC MOSFETs is analysed, and the role of gate-source voltage differences in current sharing is explored. The proposed method introduces a gate current extraction structure during the on-state and a current injection structure during the off-state to generate gate-source voltage differences between two devices, thereby eliminating the current differences caused by inconsistent device turn-on sequences. Compensation parameters are determined by analysing the mathematical model of gate-source voltage differences during switching transients. Finally, simulation analysis and experimental tests using LTspice simulation software and a parallel double-pulse test platform demonstrate that the proposed current sharing method significantly improves transient current imbalance between parallel devices.</p>","PeriodicalId":56302,"journal":{"name":"IET Power Electronics","volume":"18 1","pages":""},"PeriodicalIF":1.7,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/pel2.70030","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143749519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An Optimized Loss-Balancing Modulation Strategy for ANPC-3L Inverter","authors":"Kefeng Li, Guijing Xue, Fei Xiao, Jilong Liu, Zhuangzhi Dai, Zhiqin Mai","doi":"10.1049/pel2.70029","DOIUrl":"https://doi.org/10.1049/pel2.70029","url":null,"abstract":"<p>In existing modulation strategies for active neutral-point-clamped three-level (ANPC-3L) inverters, high-frequency and low-frequency switches are separated, with loss mainly concentrated in some fixed high-frequency operating switches, resulting in uneven loss distribution across switches among bridge arms. To address these issues, a loss-balance optimization modulation strategy is proposed. In this paper, the loss distribution of power switches under different commutation paths is analysed, and a loss-estimation model for switches is established based on the characteristics of power switches to quantify the total losses. Aimed at loss balancing for all power switches, the switching modes (commutation paths) in the modulation process are automatically selected by the proposed strategy, achieving relatively balanced losses among all switches. Experiments are carried out with an 18 kW three-phase ANPC-3L inverter. Compared with existing loss-balance strategies, the proposed strategy shows better loss (temperature) balance performance and almost equal efficiency.</p>","PeriodicalId":56302,"journal":{"name":"IET Power Electronics","volume":"18 1","pages":""},"PeriodicalIF":1.7,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/pel2.70029","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143741273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Rene A. Barrera-Cardenas, Salvatore D'Arco, Luigi Piegari, Pietro Tricoli
{"title":"Pareto-Based Design Optimisation of Hybrid Energy Storage Systems for Full-Electric Vessels","authors":"Rene A. Barrera-Cardenas, Salvatore D'Arco, Luigi Piegari, Pietro Tricoli","doi":"10.1049/pel2.70027","DOIUrl":"https://doi.org/10.1049/pel2.70027","url":null,"abstract":"<p>Full electric vessels can benefit from hybrid energy storage systems (HESS) that combine two storage technologies of different characteristics in terms of power and energy density. The optimal design of a HESS for a vessel is generally a rather complex multivariable optimization with several degrees of freedom and constraints. Indeed, the optimization should account for the operational characteristics of the storage units, including their progressive aging. Moreover, the sizing of the storage units is tightly linked to the strategy implemented in the energy management system (EMS) for allocating the power needed by the load to the storage units. This paper presents a two-stage Pareto-based design optimization procedure for HESS intended for a full-electric vessel. The methodology first identifies a Pareto front as the set of all the optimal configurations in terms of capacity of the two storage units that fulfil the operational constraints within a large discrete configuration space. These constraints account for capacity degradation and limitations in power and energy. The degrees of freedom in the EMS are included in the configuration space. A second stage identifies the optimal configuration on the Pareto front based on a defined cost function. The approach decouples the analysis of the solutions that can fulfil the operational constraints from the optimization and can be very effective in exploring the effect of several alternative cost functions on the optimal solution. Moreover, the shape of the Pareto front can offer a visual clue to the benefits offered by a hybrid storage compared to a single technology solution and on the optimization margins. The procedure is illustrated with a case of a full electric tugboat highlighting when a HESS can be beneficial and how the optimal design can be facilitated.</p>","PeriodicalId":56302,"journal":{"name":"IET Power Electronics","volume":"18 1","pages":""},"PeriodicalIF":1.7,"publicationDate":"2025-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/pel2.70027","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sajad A. Ansari, Jonathan N. Davidson, Martin P. Foster
{"title":"FEA-Based Optimisation of an Inserted-Shunt Integrated Planar Transformer for a Bidirectional CLLLC Resonant Converter","authors":"Sajad A. Ansari, Jonathan N. Davidson, Martin P. Foster","doi":"10.1049/pel2.70014","DOIUrl":"https://doi.org/10.1049/pel2.70014","url":null,"abstract":"<p>This paper presents an optimisation method for an inserted-shunt integrated planar transformer based on 3D simulation in Ansys Maxwell. The optimisation objective is enhanced efficiency and power density for the transformer. Thermal analysis verifies the optimisation to ensure the transformer's operability under limited temperature conditions when its size is reduced. The optimised integrated transformer is implemented for verification, with the presentation of experimental results, including AC resistance, efficiency, operating waveforms, and thermal imagery. Furthermore, the paper provides insight into the loss distribution of the transformer. The study shows that the optimisation enhances the power density of the inserted-shunt integrated planar transformer by 270% compared to the conventional design. Additionally, the CLLLC converter incorporating the optimised transformer achieves approximately 1.84 percentage points higher efficiency than the conventional design.</p>","PeriodicalId":56302,"journal":{"name":"IET Power Electronics","volume":"18 1","pages":""},"PeriodicalIF":1.7,"publicationDate":"2025-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/pel2.70014","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Xiuyun Zhang, Guidong Zhang, Samson S. Yu, Zhenyu Yi
{"title":"Optimized Phase-shift Tuning via Equivalent Small Parameter Modeling for Ripple Reduction in Asymmetric Parallel Multi-Module DC-DC Converters","authors":"Xiuyun Zhang, Guidong Zhang, Samson S. Yu, Zhenyu Yi","doi":"10.1049/pel2.70025","DOIUrl":"https://doi.org/10.1049/pel2.70025","url":null,"abstract":"<p>In photovoltaic power generation applications, multiple low-voltage PV modules must be boosted and connected in parallel for high power output. However, due to the variability of PV energy input, the parallel DC-DC converter modules often operate under asymmetric conditions, which deteriorates bus voltage ripple and reduces system stability and component lifespan. To address these issues, this paper proposes an optimal phase-shift modulation method with asymmetric phase shifts to effectively suppress the ripples at the point of common coupling of parallel-connected converters. To do so, a model for the output voltage ripple of boost and buck–boost parallel converter is established using the equivalent small parameter method (ESPM) with the optimal phase-shift angle determined by this modulation approach. Furthermore, a triple-loop current-sharing control strategy is implemented to ensure current sharing among the modules, enhancing the overall ripple suppression capability of the proposed modulation technique. Simulation and experimental results indicate that this integrated approach significantly improves the performance and stability of parallel converter systems.</p>","PeriodicalId":56302,"journal":{"name":"IET Power Electronics","volume":"18 1","pages":""},"PeriodicalIF":1.7,"publicationDate":"2025-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/pel2.70025","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143707266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Combined Compensation Strategy for Steady-State Performance Improvement of Proportional-Proportional-Delay Controller","authors":"Di Wu, Yan Fu, Mingming Li, Luoming OuYang","doi":"10.1049/pel2.70022","DOIUrl":"https://doi.org/10.1049/pel2.70022","url":null,"abstract":"<p>Within control system architectures, the proportional-proportional-delay (PPD) controller is theoretically characterized by enhanced dynamic responsiveness, a streamlined control structure, and reduced computational demands. Nevertheless, this control strategy demonstrates heightened dependence on system model accuracy coupled with compromised robustness, thus imposing significant constraints on its practical deployment in industrial control scenarios. To improve steady-state control performance of the PPD controller against circuit parameters variations, this paper investigates quantity relationships between circuit parameters variations and grid current amplitude changes first, and a dominant factor and some minor factors affecting the grid current are found out successfully. As a result, linear control of the PPD controller against model parameters changes has been proposed based on a linear function. Meanwhile, an integral controller composed has been integrated into the control strategy to eliminate the residual steady-state error of the proposed linear controller. Finally, a combined control structure with both linear and integral controllers has been proposed, and experimental results have been presented to verify the correctness and effectiveness of the combined control.</p>","PeriodicalId":56302,"journal":{"name":"IET Power Electronics","volume":"18 1","pages":""},"PeriodicalIF":1.7,"publicationDate":"2025-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/pel2.70022","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143698911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Finite Control Set Model Predictive Control Strategy for MMC Arm Current With DC Bus Voltage Stabilization Under Unbalanced Grid Conditions","authors":"Xiaobing Niu, Runze Qiu, Jingwei Zhu, Xin Chow","doi":"10.1049/pel2.70023","DOIUrl":"https://doi.org/10.1049/pel2.70023","url":null,"abstract":"<p>Finite Control Set Model Predictive Control (FCS-MPC) is widely used in Modular Multilevel Converters (MMC), but it faces challenges such as heavy computational burden and the complexity of designing weighting factors. Unbalanced grid voltage conditions frequently occur, and for grid-connected MMC with passive loads, the stability of the DC bus voltage is crucial. To address these issues, this paper proposes an arm current finite control set model predictive control strategy based on three-phase coupled modeling, along with a compensation mechanism for stabilizing the DC voltage. The proposed method is independent of the number of submodules and does not require weighting factor design, while effectively stabilizing the DC bus voltage without compromising the system's control objectives.</p>","PeriodicalId":56302,"journal":{"name":"IET Power Electronics","volume":"18 1","pages":""},"PeriodicalIF":1.7,"publicationDate":"2025-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/pel2.70023","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143645721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pavlo Herasymenko, Sergii Usenko, Bogdan Yarmolenko, Viktor Gurin
{"title":"Control Strategy for Modular-Structured Series-Resonant Converters: Unifying Pulse-Density Modulation and Phase-Shift Control","authors":"Pavlo Herasymenko, Sergii Usenko, Bogdan Yarmolenko, Viktor Gurin","doi":"10.1049/pel2.70020","DOIUrl":"https://doi.org/10.1049/pel2.70020","url":null,"abstract":"<p>The study proposes an advanced control technique for modular-structured series-resonant converters, unifying pulse-density modulation (PDM) and phase-shift control to mitigate output current amplitude fluctuations. Series-resonant converters, widely utilised for their efficiency in various applications, typically employ PDM to achieve zero-voltage and quasi-zero-current switching, minimising switching losses. However, these converters often encounter challenges with amplitude fluctuations in the output current, particularly during deep current regulation, which can compromise performance and lead to increased electromagnetic interference and overvoltage issues. The presented control strategy combines PDM with phase-shift control, significantly reducing these fluctuations and maintaining higher minimum peak currents. This unified approach ensures greater stability and efficiency in the converter's operation. Detailed experimental validation confirms the theoretical benefits, highlighting the proposed method's superiority over traditional PDM control techniques in achieving stable and efficient converter performance.</p>","PeriodicalId":56302,"journal":{"name":"IET Power Electronics","volume":"18 1","pages":""},"PeriodicalIF":1.7,"publicationDate":"2025-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/pel2.70020","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143602627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Iman Abdoli, Alireza Lahooti Eshkevari, Hafiz Furqan Ahmed, Mohammad Arasteh
{"title":"An Expandable Buck-Boost AC–AC Converter With Few Components, Wide Step-Down Conversion Ratio, Continuous Input Current and Common-Ground","authors":"Iman Abdoli, Alireza Lahooti Eshkevari, Hafiz Furqan Ahmed, Mohammad Arasteh","doi":"10.1049/pel2.70019","DOIUrl":"https://doi.org/10.1049/pel2.70019","url":null,"abstract":"<p>This paper proposes a new non-isolated single-phase buck-boost AC–AC converter with a reduced number of active and passive components and an improved buck-boost conversion ratio. The extension of the proposed circuit is also presented, which can generate a symmetric-bipolar buck-boost voltage. The converter achieves a wide step-down operating area due to the appropriate use of a coupled inductor, where small duty ratios are needed to obtain low step-down conversion ratios. This not only improves the efficiency but is also ideal for mitigating deep voltage sag/swell in applications such as a dynamic voltage restorer (DVR). Two out of four power switches used operate at high frequency in each input voltage half-cycle, while the other switches ensure safe commutation, which significantly reduces the switching losses compared to similar circuits. In addition, the topology has better total switch voltage stress (TSV) and switching device power (SDP) indexes than its competitors. The total volume of magnetic elements has also been improved. The converter ensures input current continuity using an input inductor and eliminates the need for additional harmonic filters. Due to its common-ground feature, a bulky line-frequency transformer can be eliminated when used in series with loads in applications such as a DVR. This article explains the operating principle of the proposed topology and evaluates its performance using a hardware prototype. Results verify the converter's operation and its superior features.</p>","PeriodicalId":56302,"journal":{"name":"IET Power Electronics","volume":"18 1","pages":""},"PeriodicalIF":1.7,"publicationDate":"2025-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://onlinelibrary.wiley.com/doi/epdf/10.1049/pel2.70019","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143594936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}