Informacije Midem-Journal of Microelectronics Electronic Components and Materials最新文献_第7页

Novel Electronically Tunable Biquadratic Mixed- Mode Universal Filter Capable of Operating in MISO and SIMO Configurations 新型电子可调谐双二次混合模式通用滤波器，可在MISO和SIMO配置下工作

IF 1.2 4区工程技术

Informacije Midem-Journal of Microelectronics Electronic Components and Materials Pub Date : 2020-11-20 DOI: 10.33180/infmidem2020.304

Mohammad Faseehuddin, Musa Ali Albrni, N. Herencsar, J. Sampe, S. Ali

{"title":"Novel Electronically Tunable Biquadratic Mixed- Mode Universal Filter Capable of Operating in MISO and SIMO Configurations","authors":"Mohammad Faseehuddin, Musa Ali Albrni, N. Herencsar, J. Sampe, S. Ali","doi":"10.33180/infmidem2020.304","DOIUrl":"https://doi.org/10.33180/infmidem2020.304","url":null,"abstract":"In this paper, a novel electronically tunable biquadratic universal mixed-mode filter is presented. The filter is based on extra X current conveyor transconductance amplifier (EXCCTA), recently introduced by authors. The proposed filter employs two EXCCTAs, two capacitors, a switch, and four resistors. The filter can work in both multi-input-single-output (MISO) and single-input-multi-output (SIMO) configurations without change in its structure. The filter provides low-pass (LP), high-pass (HP), band-pass (BP), band-reject (BR) and all-pass (AP) responses in voltage-mode (VM), current-mode (CM), transimpedance-mode (TIM), and transadmittance-mode (TAM). The attractive features of the filter include (i) ability to operate in both MISO and SIMO configurations in all four modes, (ii) no requirement of capacitive matching, (iii) high output impedance in SIMO (CM & TAM) configuration, (iv) tunability of quality factor ( Q ) independent of natural frequency ( ) in MISO & SIMO configurations, (v) use of grounded capacitors in SIMO configuration, (vi) low output impedance for MISO (VM & TIM), (vii) high output impedance explicit current output for MISO (CM & TAM), and (viii) no requirement for double/negative input signals (voltage/current) in MISO configuration. The non-ideal gain and sensitivity analysis is also carried out to study the effects of process variations and passive components spread on filter performance. The filter is designed in Cadence Virtuoso using Silterra Malaysia 0.18µm PDK. The complete layout of the EXCCTA is designed and the parasitic extraction is done. The filter is tested at a supply voltage of ±1.25 V and the obtained results validate the theoretical findings.","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"17 1","pages":"189-204"},"PeriodicalIF":1.2,"publicationDate":"2020-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85421953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Modeling of Static Negative Bias Temperature Stressing in p-channel VDMOSFETs using Least Square Method p沟道vdmosfet静态负偏置温度应力的最小二乘法建模

IF 1.2 4区工程技术

Informacije Midem-Journal of Microelectronics Electronic Components and Materials Pub Date : 2020-11-20 DOI: 10.33180/infmidem2020.305

N. Mitrović, D. Danković, Branislav Ranđelović, Z. Prijić, N. Stojadinovic

引用次数: 1

On the Finite-Element Analysis of Resonance MEMS Structures based on Acoustic Lamb Waves 基于Lamb波的谐振MEMS结构有限元分析

IF 1.2 4区工程技术

Informacije Midem-Journal of Microelectronics Electronic Components and Materials Pub Date : 2020-11-20 DOI: 10.33180/infmidem2020.303

P. Marinushkin, A. Levitsky, Fyodor Zograf, V. A. Bakhtina

引用次数: 1

A Computationally Efficient 11 Band Non-Uniform Filter Bank for Hearing Aids Targeting Moderately Sloping Sensorineural Hearing Loss 针对中度倾斜型感音神经性听力损失的助听器计算高效的11波段非均匀滤波器组

IF 1.2 4区工程技术

Informacije Midem-Journal of Microelectronics Electronic Components and Materials Pub Date : 2020-11-20 DOI: 10.33180/infmidem2020.301

S. Philip, S. Palaniswami, Harikirubha Sivakumar

引用次数: 1

CMOS High-Performance 5-2 and 6-2 Compressors for High-Speed Parallel Multipliers 用于高速并行乘法器的CMOS高性能5-2和6-2压缩机

IF 1.2 4区工程技术

Informacije Midem-Journal of Microelectronics Electronic Components and Materials Pub Date : 2020-09-22 DOI: 10.33180/infmidem2020.204

Ali Rahnamaei

{"title":"CMOS High-Performance 5-2 and 6-2 Compressors for High-Speed Parallel Multipliers","authors":"Ali Rahnamaei","doi":"10.33180/infmidem2020.204","DOIUrl":"https://doi.org/10.33180/infmidem2020.204","url":null,"abstract":"In this article, the design fashion of high-speed 5-2 and 6-2 compressors along with their analysis, has been discussed. With the help of combinational logic consisting of the 4-2 compressor and 3-2 counter structures, a high-performance structure for 6-2 compressor has been obtained which shows significant speed improvement over previous architectures. The optimization is achieved by reducing the carry rippling issue between adjacent compressor blocks. Also, the proposed 6-2 compressor with some modifications will turn into a 5-2 compressor in which latency of the critical path has considerably been reduced, illustrating the superiority of designed circuits. The delay of proposed 5-2 and 6-2 structures is equal to 3.5 and 4 XOR logic gates, respectively, demonstrating speed boosting of 15% and 20% compared to the best-reported architectures. In addition, the power consumption and transistor count of proposed circuits are in reasonable level. Therefore, by considering the Power-Delay Product (PDP), our work will be a good choice for high-speed parallel multiplier design. Post-layout simulation results based on TSMC 90nm standard CMOS process and 0.9V power supply have been presented to confirm the correct functionality of the implemented compressors. These results have also been used as a fair comparison infrastructure between the proposed works and redesignated architectures of previously reported schemes.","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"14 1","pages":"115-124"},"PeriodicalIF":1.2,"publicationDate":"2020-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85354111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Real-time, Cuff-less and Non-invasiveBlood Pressure Monitoring 实时、无袖带、无创血压监测

IF 1.2 4区工程技术

Informacije Midem-Journal of Microelectronics Electronic Components and Materials Pub Date : 2020-09-22 DOI: 10.33180/infmidem2020.202

Alireza Abolhasani, Morteza Mousazadeh, A. Khoei

{"title":"Real-time, Cuff-less and Non-invasiveBlood Pressure Monitoring","authors":"Alireza Abolhasani, Morteza Mousazadeh, A. Khoei","doi":"10.33180/infmidem2020.202","DOIUrl":"https://doi.org/10.33180/infmidem2020.202","url":null,"abstract":"In in this study ultrasonic method was applied for measuring blood pressure (BP). First, a novel method is proposed to measure mean arterial pressure (MAP), diastolic blood pressure (DBP) and systolic blood pressure (SBP) using ultrasonic sensors. The proposed algorithm is implemented by measuring the diameter of the artery and the speed of blood flow based on Doppler physical phenomena so the blood pressure can be calculated. The results of the proposed algorithm for MAP, SBP, and DBP hypertension analyses were evaluated with the results of Association for the Advancement of Medical Instrumentation (AAMI standard) for all three cases and their mean error rate for the worst case was -0.233mmHg and the standard deviation for 422 samples taken from individuals in the worst case was 4.53 mmHg that meets the standard requirements. Also, according to the British Hypertension Society (BHS) standard, a proposed algorithm for estimating blood pressure for all three cases of MAP, DBP, and SBP has Grade A, indicating high accuracy in measuring and using the most effective variables in the diagnosis of hypertension in the human body. The proposed algorithm in BP estimation is non-invasive, cuff-less, no calibration, and only based on using the ultrasonic sensor.","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"34 1","pages":"87-104"},"PeriodicalIF":1.2,"publicationDate":"2020-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78947114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

CMOS series-shunt single-pole double-throw transmit/receive switch and low noise amplifier design for internet of things based radio frequency identification devices 基于物联网射频识别设备的CMOS串联分流单极双掷发射/接收开关和低噪声放大器设计

IF 1.2 4区工程技术

Informacije Midem-Journal of Microelectronics Electronic Components and Materials Pub Date : 2020-09-22 DOI: 10.33180/infmidem2020.203

M. Bhuiyan

{"title":"CMOS series-shunt single-pole double-throw transmit/receive switch and low noise amplifier design for internet of things based radio frequency identification devices","authors":"M. Bhuiyan","doi":"10.33180/infmidem2020.203","DOIUrl":"https://doi.org/10.33180/infmidem2020.203","url":null,"abstract":"The incompatibility between current RFID standards has led to the need for universal and Wi-Fi compatible RFID for IoT applications. Such a universal RFID requires an SPDT and an LNA to direct and amplify the received raw signal by the antenna. The SPDT suffers from low isolation, high insertion loss and low power handling capacity whereas the LNA suffers from bulky die area, lesser Q factor, limited tuning flexibility etc. because of passive inductor usage in current generation of devices. In this research, nano-CMOS inductorless SPDT and LNA designs are proposed. The SPDT adopts a series-shunt topology along with parallel resonant circuits and resistive body floating in order to achieve improved insertion loss and isolation performance whereas the LNA design is implemented with the gyrator concept in which the frequency selective tank circuit is formed with an active inductor accompanied by the buffer circuits. The post-layout simulation results, utilizing 90nm CMOS process of cadence virtuoso, exhibit that our SPDT design accomplishes 0.83dB insertion loss, a 45.3dB isolation, and a 11.3dBm power-handling capacity whereas the LNA achieves a peak gain of 33dB, bandwidth of 30MHz and NF of 6.6dB at 2.45GHz center frequency. Both the SPDT and LNA have very compact layout which are 0.003mm 2 and 127.7 μm 2 , respectively. Such SPDT and LNA design will boost the widespread adaptation of Wi-Fi-compatible IoT RFID technology.","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"9 1","pages":"105-114"},"PeriodicalIF":1.2,"publicationDate":"2020-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90348406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

DTMOS Based High Bandwidth Four-Quadrant Analog Multiplier 基于DTMOS的高带宽四象限模拟乘法器

IF 1.2 4区工程技术

Informacije Midem-Journal of Microelectronics Electronic Components and Materials Pub Date : 2020-09-22 DOI: 10.33180/infmidem2020.206

M. Başak, E. Özer, F. Kaçar, Deniz Ozenli

引用次数: 3

Single VDGA-Based Dual-Mode Multifunction Biquadratic Filter and Quadrature Sinusoidal Oscillator 基于单vdga的双模多功能双二次滤波器和正交正弦振荡器

IF 1.2 4区工程技术

Informacije Midem-Journal of Microelectronics Electronic Components and Materials Pub Date : 2020-09-22 DOI: 10.33180/infmidem2020.205

O. Channumsin

引用次数: 6

Hardware Implementation of Residue Multipliers based Signed RNS Processor for Cryptosystems 基于残数乘法器的签名RNS处理器的硬件实现

IF 1.2 4区工程技术

Informacije Midem-Journal of Microelectronics Electronic Components and Materials Pub Date : 2020-09-20 DOI: 10.33180/infmidem2020.201

Elango Sekar, Sampath Palaniswami

{"title":"Hardware Implementation of Residue Multipliers based Signed RNS Processor for Cryptosystems","authors":"Elango Sekar, Sampath Palaniswami","doi":"10.33180/infmidem2020.201","DOIUrl":"https://doi.org/10.33180/infmidem2020.201","url":null,"abstract":"The Residue Number System (RNS) characterize large integer numbers into smaller residues using moduli sets to enhance the performance of digital cryptosystems. A parallel Signed Residue Multiplication (SRM) algorithm, VLSI hierarchical array architecture for balanced (2 n -1, 2 n , 2 n +1) and unbalanced (2 k -1, 2 k , 2 k +1) word-length moduli are proposed which is capable of handling signed input numbers. Balanced 2 n -1 SRM is used as a reference to design an unbalanced 2 k -1 and 2 k +1. The synthesized results show that the proposed 2 n -1 SRM architecture achieves 17% of the area, 26% of speed and 24% of Power Delay Product (PDP) improvement compared to the Modified Booth Encoded (MBE) architectures discussed in the literature. The proposed 2 n +1 SRM architecture achieves 23% of the area, 20% of speed and 22% of PDP improvement compared to recent counterparts. There is a significant improvement in the results due to the fully parallel hierarchical approach adopted for the design which is hardly attempted for signed numbers using array architectures. Finally, the proposed SRM modules are used to design {2 n -1, 2 n , 2 n +1} special moduli set based RNS processor and the real-time verification is performed on Zynq (XC7Z020CLG484-1) Field Programmable Gate Array (FPGA).","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"23 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2020-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78178804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2